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📄 mux_hib.tdf

📁 基于QUARTUSII软件 实现FPGA(ATERA CYCLONE II系列)与SD卡SD模式通信源码
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--lpm_mux CBX_DECLARE_ALL_CONNECTED_PORTS="OFF" DEVICE_FAMILY="Cyclone II" LPM_SIZE=2 LPM_WIDTH=8 LPM_WIDTHS=1 data result sel
--VERSION_BEGIN 5.0 cbx_lpm_mux 2004:12:13:14:16:38:SJ cbx_mgl 2005:04:13:17:26:48:SJ  VERSION_END


--  Copyright (C) 1988-2005 Altera Corporation
--  Your use of Altera Corporation's design tools, logic functions 
--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files any of the foregoing 
--  (including device programming or simulation files), and any 
--  associated documentation or information are expressly subject 
--  to the terms and conditions of the Altera Program License 
--  Subscription Agreement, Altera MegaCore Function License 
--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.



--synthesis_resources = lut 8 
SUBDESIGN mux_hib
( 
	data[15..0]	:	input;
	result[7..0]	:	output;
	sel[0..0]	:	input;
) 
VARIABLE 
	result_node[7..0]	: WIRE;
	sel_node[0..0]	: WIRE;
	w_data147w[1..0]	: WIRE;
	w_data161w[1..0]	: WIRE;
	w_data173w[1..0]	: WIRE;
	w_data185w[1..0]	: WIRE;
	w_data197w[1..0]	: WIRE;
	w_data209w[1..0]	: WIRE;
	w_data221w[1..0]	: WIRE;
	w_data233w[1..0]	: WIRE;
	w_result148w	: WIRE;
	w_result154w	: WIRE;
	w_result162w	: WIRE;
	w_result168w	: WIRE;
	w_result174w	: WIRE;
	w_result180w	: WIRE;
	w_result186w	: WIRE;
	w_result192w	: WIRE;
	w_result198w	: WIRE;
	w_result204w	: WIRE;
	w_result210w	: WIRE;
	w_result216w	: WIRE;
	w_result222w	: WIRE;
	w_result228w	: WIRE;
	w_result234w	: WIRE;
	w_result240w	: WIRE;

BEGIN 
	result[] = result_node[];
	result_node[] = ( w_result234w, w_result222w, w_result210w, w_result198w, w_result186w, w_result174w, w_result162w, w_result148w);
	sel_node[] = ( sel[0..0]);
	w_data147w[] = ( data[8..8], data[0..0]);
	w_data161w[] = ( data[9..9], data[1..1]);
	w_data173w[] = ( data[10..10], data[2..2]);
	w_data185w[] = ( data[11..11], data[3..3]);
	w_data197w[] = ( data[12..12], data[4..4]);
	w_data209w[] = ( data[13..13], data[5..5]);
	w_data221w[] = ( data[14..14], data[6..6]);
	w_data233w[] = ( data[15..15], data[7..7]);
	w_result148w = w_result154w;
	w_result154w = ((sel_node[] & w_data147w[1..1]) # ((! sel_node[]) & w_data147w[0..0]));
	w_result162w = w_result168w;
	w_result168w = ((sel_node[] & w_data161w[1..1]) # ((! sel_node[]) & w_data161w[0..0]));
	w_result174w = w_result180w;
	w_result180w = ((sel_node[] & w_data173w[1..1]) # ((! sel_node[]) & w_data173w[0..0]));
	w_result186w = w_result192w;
	w_result192w = ((sel_node[] & w_data185w[1..1]) # ((! sel_node[]) & w_data185w[0..0]));
	w_result198w = w_result204w;
	w_result204w = ((sel_node[] & w_data197w[1..1]) # ((! sel_node[]) & w_data197w[0..0]));
	w_result210w = w_result216w;
	w_result216w = ((sel_node[] & w_data209w[1..1]) # ((! sel_node[]) & w_data209w[0..0]));
	w_result222w = w_result228w;
	w_result228w = ((sel_node[] & w_data221w[1..1]) # ((! sel_node[]) & w_data221w[0..0]));
	w_result234w = w_result240w;
	w_result240w = ((sel_node[] & w_data233w[1..1]) # ((! sel_node[]) & w_data233w[0..0]));
END;
--VALID FILE

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