test.fit.rpt

基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）与SD卡SD模式通信源码

Fitter report for test
Wed Nov 07 11:05:54 2007
Version 5.0 Build 148 04/26/2005 SJ Full Version


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; Table of Contents ;
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  1. Legal Notice
  2. Fitter Summary
  3. Fitter Settings
  4. Fitter Device Options
  5. Fitter Equations
  6. Pin-Out File
  7. Fitter Resource Usage Summary
  8. Input Pins
  9. Output Pins
 10. Bidir Pins
 11. I/O Bank Usage
 12. All Package Pins
 13. Output Pin Default Load For Reported TCO
 14. Fitter Resource Utilization by Entity
 15. Delay Chain Summary
 16. Pad To Core Delay Chain Fanout
 17. Control Signals
 18. Global & Other Fast Signals
 19. Non-Global High Fan-Out Signals
 20. Fitter RAM Summary
 21. Interconnect Usage Summary
 22. LAB Logic Elements
 23. LAB-wide Signals
 24. LAB Signals Sourced
 25. LAB Signals Sourced Out
 26. LAB Distinct Inputs
 27. Fitter Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------------------+
; Fitter Summary                                                                ;
+------------------------------------+------------------------------------------+
; Fitter Status                      ; Successful - Wed Nov 07 11:05:53 2007    ;
; Quartus II Version                 ; 5.0 Build 148 04/26/2005 SJ Full Version ;
; Revision Name                      ; test                                     ;
; Top-level Entity Name              ; test                                     ;
; Family                             ; Cyclone II                               ;
; Device                             ; EP2C35F484C8                             ;
; Timing Models                      ; Preliminary                              ;
; Total logic elements               ; 2,181 / 33,216 ( 6 % )                   ;
; Total pins                         ; 180 / 322 ( 55 % )                       ;
; Total virtual pins                 ; 0                                        ;
; Total memory bits                  ; 148,480 / 483,840 ( 30 % )               ;
; Embedded Multiplier 9-bit elements ; 0 / 70 ( 0 % )                           ;
; Total PLLs                         ; 0 / 4 ( 0 % )                            ;