test.map.summary

来自「基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）」· SUMMARY 代码 · 共 16 行

Flow Status : Successful - Wed Nov 07 11:04:41 2007
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : test
Top-level Entity Name : test
Family : Cyclone II
Device : EP2C35F484C8
Timing Models : Preliminary
Met timing requirements : N/A
Total combinational functions : 1795
Total registers : 1620
Total pins : 184
Total virtual pins : 0
Total memory bits : 148,480
Embedded Multiplier 9-bit elements : 0
Total PLLs : 0