bidirec.v

来自「基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）」· Verilog 代码 · 共 15 行

module bidirec (oe, clk, inp, outp);

// Port Declaration

input   oe;
input   clk;
input   inp;
output  outp;

reg     outp;

always @ (posedge clk)
	outp = oe ? inp : 1'bZ ;
	
endmodule