fifo_control.v

来自「基于QUARTUSII软件 实现FPGA（ATERA CYCLONE II系列）」· Verilog 代码 · 共 80 行

/**************************************************

	函数名：fifo_control
	功  能：实现对fifo的控制
	参  数：
	
**************************************************/

module fifo_control(enable,
					clk,
					ram1_ren,
					ram2_ren,
					data_in,
					data_out,
					fifo_wen,
					rdaddress
					);
parameter wd=32;
input   enable,ram1_ren,ram2_ren,clk;
input   [wd-1:0]data_in;

output  fifo_wen;
output  [wd-1:0]data_out;
output  [3:0]rdaddress;
reg     [4:0]address;
reg     fifo_wen,fifo_wen_temp,fifo_ren,flag;

assign  rdaddress=address[3:0];
assign  data_out=data_in;

always @(posedge clk)
	fifo_wen<=fifo_wen_temp;
	
	
always @(posedge clk)
	begin
	if(!enable)
		begin
		fifo_wen_temp<=1'b1;
		fifo_ren<=1'b1;
		address<=5'b0;
		flag<=1'b0;
		end
	else
		begin
		fifo_ren<=1'b1;
		case({ram1_ren,ram2_ren})
		2'b10:  if(address<16 && flag==1'b0)
					begin
					address<=address+5'b00001;
					fifo_wen_temp<=1'b0;
					end
				else
					begin
					flag<=1'b1;
					fifo_wen_temp<=1'b1;
					address<=5'b0;
					end
		2'b01:  if(address<16 && flag==1'b1)
					begin
					address<=address+5'b00001;
					fifo_wen_temp<=1'b0;
					end
				else
					begin
					flag<=1'b0;
					fifo_wen_temp<=1'b1;
					address<=5'b0;
					end
		default:begin
				fifo_wen_temp<=1'b1;
				fifo_ren<=1'b1;
				address<=5'b0;
				end
		endcase
		end
	end
	

endmodule