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📄 hidtherm.lst

📁 Cypress USB HID code
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CYASM Version 1.96 
(C) 1998,1999,2000,2001 Cypress Semiconductor Corp.

                ;******************************************************
                ;
                ;       file:           Thermometer application board firmware
                ;       Date:           03/22/2002
                ;       Description:This code provides the functionality  
                ;                               for a USB thermometer application.
                ;       Target:         Cypress CY7C63743
                ;
                ; Overview
                ;               There are four main sub-systems: 
                ;                       * USB 
                ;                       * Thermometer 
                ;                       * LED 
                ;                       * Button 
                ;
                ;       The system is started in the reset() routine at reset. 
                ;               This routine initializes the USB variables, the IO ports, 
                ;               the Thermometer logic, and the data space. All USB 
                ;               communication occurs on an interrupt basis.  First, 
                ;               reset() loops waiting for a USB reset.  After receiving 
                ;               a USB reset, Main() enables the Endpoint 0 interrupt and 
                ;       loops waiting for Setups which ultimately will the 
                ;               result in the device being enumerated.
                ;               Once the device has been enumerated on the USB, the main 
                ;               loop waits 10ms, polls the thermometer, updates the LED, 
                ;               and initializes endpoint 1 if appropriate.
                ; USB
                ;               Endpoint 0 is used to support Control Transfers and 
                ;               vendor specific requests.  During enumeration setup
                ;               commands are sent to endpoint1 to initialize the
                ;               USB device and to extract configuration information
                ;               from the device
                ;
                ;               Endpoint 1 is used to transfer interrupt data back to
                ;               the host.  In this case we transfer data from the 
                ;               DS1722 thermometer chip back to the host. 
                ; Thermometer
                ;               At power up the DS1722 thermometer is initialized.
                ;               After the device is configured on the USB, every
                ;               10ms we transfer the output data of the thermometer
                ;               to the host when we receive an IN on endpoint1 
                ; LED
                ;               At power up the ACTIVE LED is turned on.  After the 
                ;               device is configured, the ENUM LED is turned on.  
                ;               The ENUM LED is PWM'd with a period of 16ms.  You can 
                ;               set the PWM rate in the host application. 
                ; Button
                ;               The button S5 is measured every millisecond and debounced 
                ;               over 15ms.  The switch on/off data is sent to the host
                ;               every time we get an IN on endpoint1.
                ;
                ; Endpoint1 packet definition
                ;
                ; Byte  Usage
                ;  0    Signed integer part of temperature
                ;  1    Fractional part of temperature
                ;  2    Button status
                ;  3    Port 0 value                                    (For host application testing)
                ;  4    Port 1 value                                    (For host application testing)
                ;  5    Endpoint 0 interrupt counter    (For host application testing)
                ;  6    Endpoint 1 interrupt counter    (For host application testing)
                ;  7    GPIO interrupt counter              (For host application testing)
                ;
                ;
                ; Port Usage
                ;
                ;                        -------------------
                ;       RFIN    | P0[0]         P0[4]   |       TEMP_SS
                ;                       | P0[1]         P0[5]   |       TEMP/EE_SI
                ;       RFOUT   | P0[2]         P0[6]   |       TEMP/EE_SO
                ;       EE_SS   | P0[3]         P0[7]   |       TEMP/EE_SCK
                ;       AUX02   | P1[0]         P1[1]   |       
                ;       AUX01   | P1[2]         P1[3]   |       SWITCH5
                ;       ENUM    | P1[4]         P1[5]   |       SWITCH4
                ;       ACTIVE  | P1[6]         P1[7]   |       SWITCH3
                ;       GND             | VSS           D+/SCLK |       USB D+ / PS2 SCLK
                ;       GND             | VPP           D-/SDATA|       USB D- / PS2 SDATA
                ;       PULLUP  | VREG          VCC             |       +5
                ;                       | XTALIN        XTALOUT |
                ;                        -------------------
                ;
                ; Revisions:
                ;                       3-22-2002       SEA             Creation
                ;
                ;**********************************************************
                ;
                ;               Copyright 2000 Cypress Semiconductor
                ;       This code is provided by Cypress as a reference.  Cypress 
                ;       makes no claims or warranties to this firmware's 
                ;       suitability for any application. 
                ;
                ;********************************************************** 
                
                ;**************** assembler directives ***************** 
                
0000                    CPU     63742
                
0000                    XPAGEON
                
                ;**************************************
                ; Processor specific definitions
                
00E8=           ep2_dmabuff:                            equ     E8h
00E8=           ep2_dmabuff0:                           equ     ep2_dmabuff+0
00E9=           ep2_dmabuff1:                           equ     ep2_dmabuff+1
00EA=           ep2_dmabuff2:                           equ     ep2_dmabuff+2
00EB=           ep2_dmabuff3:                           equ     ep2_dmabuff+3
00EC=           ep2_dmabuff4:                           equ     ep2_dmabuff+4
00ED=           ep2_dmabuff5:                           equ     ep2_dmabuff+5
00EE=           ep2_dmabuff6:                           equ     ep2_dmabuff+6
00EF=           ep2_dmabuff7:                           equ     ep2_dmabuff+7
                
00F0=           ep1_dmabuff:                            equ     F0h
00F0=           ep1_dmabuff0:                           equ     ep1_dmabuff+0
00F1=           ep1_dmabuff1:                           equ     ep1_dmabuff+1
00F2=           ep1_dmabuff2:                           equ     ep1_dmabuff+2
00F3=           ep1_dmabuff3:                           equ     ep1_dmabuff+3
00F4=           ep1_dmabuff4:                           equ     ep1_dmabuff+4
00F5=           ep1_dmabuff5:                           equ     ep1_dmabuff+5
00F6=           ep1_dmabuff6:                           equ     ep1_dmabuff+6
00F7=           ep1_dmabuff7:                           equ     ep1_dmabuff+7
                
00F8=           ep0_dmabuff:                            equ     F8h
00F8=           ep0_dmabuff0:                           equ     ep0_dmabuff+0
00F9=           ep0_dmabuff1:                           equ     ep0_dmabuff+1
00FA=           ep0_dmabuff2:                           equ     ep0_dmabuff+2
00FB=           ep0_dmabuff3:                           equ     ep0_dmabuff+3
00FC=           ep0_dmabuff4:                           equ     ep0_dmabuff+4
00FD=           ep0_dmabuff5:                           equ     ep0_dmabuff+5
00FE=           ep0_dmabuff6:                           equ     ep0_dmabuff+6
00FF=           ep0_dmabuff7:                           equ     ep0_dmabuff+7
                
                
                
                ;**************************************
                ; register definitions
                
0000=           port0:                                                          equ     00h ; GPIO data port 0
0001=           port1:                                                          equ     01h ; GPIO data port 1
0002=           port2:                                                          equ     02h ; GPIO data port 2
0020=                   SCLK:                                   equ     20h
0020=                   DPLUS:                                  equ     20h
0010=                   SDATA:                                  equ     10h
0010=                   DMINUS:                                 equ     10h
0002=                   XTALIN:                                 equ     02h
0001=                   VREG:                                   equ     01h
                
0004=           port0_int:                                                      equ     04h ; Interrupt enable for Port 0
0005=           port1_int:                                                      equ     05h ; Interrupt enable for Port 1
0006=           port0_int_polarity:                                     equ     06h ; Interrupt polarity for Port 0
0007=           port1_int_polarity:                                     equ     07h ; Interrupt polarity for Port 1
                
000A=           port0_mode0:                                            equ     0Ah ; Mode Configuration 0 for Port 0
000B=           port0_mode1:                                            equ     0Bh ; Mode Configuration 1 for Port 0
000C=           port1_mode0:                                            equ     0Ch ; Mode Configuration 0 for Port 1
000D=           port1_mode1:                                            equ     0Dh ; Mode Configuration 1 for Port 1
                
0010=           usb_address:                                            equ     10h ; USB device address
0080=                   ADDRESS_ENABLE:                 equ     80h
007F=                   ADDRESS_MASK:                   equ     7Fh
                
0011=           ep0_count:                                                      equ     11h     ; Endpoint 0 counter
0080=                   DATA_TOGGLE:                    equ     80h
0040=                   DATA_VALID:                             equ     40h
000F=                   BYTE_COUNT:                             equ     0Fh
0012=           ep0_mode:                                                       equ     12h ; Endpoint 0 configuration
0080=                   EP0_SETUP:                              equ     80h
0040=                   EP0_IN:                                 equ     40h
0020=                   EP0_OUT:                                equ     20h
0010=                   EP0_ACK:                                equ     10h
000F=                   MODE_MASK:                              equ     0Fh
0013=           ep1_count:                                                      equ     13h ; Endpoint 1 counter
0014=           ep1_mode:                                                       equ     14h ; Endpoint 1 configuration
0015=           ep2_count:                                                      equ     15h ; Endpoint 2 counter
0016=           ep2_mode:                                                       equ     16h ; Endpoint 2 configuration
0080=                   EP_STALL:                               equ     80h
0010=                   EP_ACK:                                 equ     10h
                
001F=           usb_status:                                                     equ     1Fh ; USB upstream status and control
0080=                   PS2_PULLUP:                             equ     80h
0040=                   VREG_ENABLE:                    equ     40h
0020=                   USB_PS2_MODE:                   equ     20h
0008=                   BUS_ACTIVITY:                   equ     08h
0004=                   CONTROL2:                               equ     04h
0002=                   CONTROL1:                               equ     02h
0001=                   CONTROL0:                               equ     01h
                
0000=                   NOT_FORCING:                    equ     00h
0001=                   FORCE_K:                                equ     01h
0002=                   FORCE_J:                                equ     02h
0003=                   FORCE_SE0:                              equ     03h
0004=                   FORCEBOTH_LOW:                  equ     04h
0005=                   FORCESDATA_LOW:                 equ     05h
0006=                   FORCESCLK_LOW:                  equ     06h
0007=                   FORCE_HIZ:                              equ     07h
                
0020=           global_int:                                                     equ     20h ; Global interrupt enable
0080=                   WAKEUP_INT:                             equ     80h
0040=                   GPIO_INT:                               equ     40h
0020=                   CAPTUREB_INT:                   equ     20h
0010=                   CAPTUREA_INT:                   equ     10h
0008=                   SPI_INT:                                equ     08h
0004=                   1MS_INT:                                equ     04h
0002=                   128US_INT:                              equ     02h
0001=                   USB_RESET_INT:                  equ     01h
                
0021=           endpoint_int:                                           equ     21h ; USB endpoint interrupt enable
0004=                   EP2_INT:                                equ     04h
0002=                   EP1_INT:                                equ     02h
0001=                   EP0_INT:                                equ     01h
                
0024=           timer_lsb:                                                      equ     24h ; Lower eight bits of timer
0025=           timer_msb:                                                      equ     25h ; Upper six bits of timer
0026=           watchdog:                                                       equ     26h ; Clear watchdog Timer
                
0040=           capturea_rising:                                        equ     40h ; Capture timer A rising register
0041=           capturea_falling:                                       equ     41h ; Capture timer A falling register

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