xkcon.tan.qmsg

用VHDL语言写的程序实例

{ "Info" "ITDB_TSU_RESULT" "outpa\[3\]~reg0 databus\[3\] wr 4.000 ns register " "Info: tsu for register \"outpa\[3\]~reg0\" (data pin = \"databus\[3\]\", clock pin = \"wr\") is 4.000 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "23.000 ns + Longest pin register " "Info: + Longest pin to register delay is 23.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns databus\[3\] 1 PIN PIN_57 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PIN_57; Fanout = 1; PIN Node = 'databus\[3\]'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { databus[3] } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns databus\[3\]~4 2 COMB IO88 5 " "Info: 2: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = IO88; Fanout = 5; COMB Node = 'databus\[3\]~4'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "2.000 ns" { databus[3] databus[3]~4 } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 31 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 23.000 ns outpa\[3\]~reg0 3 REG LC25 2 " "Info: 3: + IC(2.000 ns) + CELL(19.000 ns) = 23.000 ns; Loc. = LC25; Fanout = 2; REG Node = 'outpa\[3\]~reg0'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { databus[3]~4 outpa[3]~reg0 } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 198 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 91.30 % " "Info: Total cell delay = 21.000 ns ( 91.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.70 % " "Info: Total interconnect delay = 2.000 ns ( 8.70 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { databus[3] databus[3]~4 outpa[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { databus[3] databus[3]~4 outpa[3]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 19.000ns } } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns + " "Info: + Micro setup delay of destination is 4.000 ns" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 198 -1 0 } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr destination 23.000 ns - Shortest register " "Info: - Shortest clock path from clock \"wr\" to destination register is 23.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns wr 1 CLK PIN_67 35 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_67; Fanout = 35; CLK Node = 'wr'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { wr } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 23.000 ns outpa\[3\]~reg0 2 REG LC25 2 " "Info: 2: + IC(2.000 ns) + CELL(19.000 ns) = 23.000 ns; Loc. = LC25; Fanout = 2; REG Node = 'outpa\[3\]~reg0'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { wr outpa[3]~reg0 } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 198 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 91.30 % " "Info: Total cell delay = 21.000 ns ( 91.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.70 % " "Info: Total interconnect delay = 2.000 ns ( 8.70 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr outpa[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out outpa[3]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 19.000ns } } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { databus[3] databus[3]~4 outpa[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { databus[3] databus[3]~4 outpa[3]~reg0 } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 19.000ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr outpa[3]~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out outpa[3]~r