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📄 xkcon.tan.qmsg

📁 用VHDL语言写的程序实例
💻 QMSG
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{ "Info" "ITAN_NO_REG2REG_EXIST" "ale " "Info: No valid register-to-register data paths exist for clock \"ale\"" {  } {  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "clk8mhz register count_ad\[0\] register count_ad\[0\] 5.0 ns " "Info: Minimum slack time is 5.0 ns for clock \"clk8mhz\" between source register \"count_ad\[0\]\" and destination register \"count_ad\[0\]\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.000 ns + Shortest register register " "Info: + Shortest register to register delay is 8.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns count_ad\[0\] 1 REG LC32 73 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC32; Fanout = 73; REG Node = 'count_ad\[0\]'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { count_ad[0] } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 61 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(8.000 ns) 8.000 ns count_ad\[0\] 2 REG LC32 73 " "Info: 2: + IC(0.000 ns) + CELL(8.000 ns) = 8.000 ns; Loc. = LC32; Fanout = 73; REG Node = 'count_ad\[0\]'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "8.000 ns" { count_ad[0] count_ad[0] } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 61 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "8.000 ns 100.00 % " "Info: Total cell delay = 8.000 ns ( 100.00 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "8.000 ns" { count_ad[0] count_ad[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { count_ad[0] count_ad[0] } { 0.0ns 0.0ns } { 0.0ns 8.0ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "3.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 3.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk8mhz 125.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"clk8mhz\" is 125.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk8mhz 125.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"clk8mhz\" is 125.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk8mhz destination 25.000 ns + Longest register " "Info: + Longest clock path from clock \"clk8mhz\" to destination register is 25.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk8mhz 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk8mhz'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { clk8mhz } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns clk200khz 2 REG LC125 28 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC125; Fanout = 28; REG Node = 'clk200khz'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "1.000 ns" { clk8mhz clk200khz } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 25.000 ns count_ad\[0\] 3 REG LC32 73 " "Info: 3: + IC(2.000 ns) + CELL(19.000 ns) = 25.000 ns; Loc. = LC32; Fanout = 73; REG Node = 'count_ad\[0\]'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { clk200khz count_ad[0] } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 61 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.000 ns 92.00 % " "Info: Total cell delay = 23.000 ns ( 92.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.00 % " "Info: Total interconnect delay = 2.000 ns ( 8.00 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk200khz count_ad[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk200khz count_ad[0] } { 0.0ns 0.0ns 0.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 19.0ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk8mhz source 25.000 ns - Shortest register " "Info: - Shortest clock path from clock \"clk8mhz\" to source register is 25.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk8mhz 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk8mhz'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { clk8mhz } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns clk200khz 2 REG LC125 28 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC125; Fanout = 28; REG Node = 'clk200khz'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "1.000 ns" { clk8mhz clk200khz } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 25.000 ns count_ad\[0\] 3 REG LC32 73 " "Info: 3: + IC(2.000 ns) + CELL(19.000 ns) = 25.000 ns; Loc. = LC32; Fanout = 73; REG Node = 'count_ad\[0\]'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { clk200khz count_ad[0] } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 61 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.000 ns 92.00 % " "Info: Total cell delay = 23.000 ns ( 92.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.00 % " "Info: Total interconnect delay = 2.000 ns ( 8.00 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk200khz count_ad[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk200khz count_ad[0] } { 0.0ns 0.0ns 0.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 19.0ns } } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk200khz count_ad[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk200khz count_ad[0] } { 0.0ns 0.0ns 0.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 19.0ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk200khz count_ad[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk200khz count_ad[0] } { 0.0ns 0.0ns 0.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 19.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 61 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 61 -1 0 } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk200khz count_ad[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk200khz count_ad[0] } { 0.0ns 0.0ns 0.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 19.0ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk200khz count_ad[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk200khz count_ad[0] } { 0.0ns 0.0ns 0.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 19.0ns } } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "8.000 ns" { count_ad[0] count_ad[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "8.000 ns" { count_ad[0] count_ad[0] } { 0.0ns 0.0ns } { 0.0ns 8.0ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk200khz count_ad[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk200khz count_ad[0] } { 0.0ns 0.0ns 0.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 19.0ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk200khz count_ad[0] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk200khz count_ad[0] } { 0.0ns 0.0ns 0.0ns 2.0ns } { 0.0ns 3.0ns 1.0ns 19.0ns } } }  } 0}
{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "wr register begin_ad register begin_ad 18.0 ns " "Info: Minimum slack time is 18.0 ns for clock \"wr\" between source register \"begin_ad\" and destination register \"begin_ad\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.000 ns + Shortest register register " "Info: + Shortest register to register delay is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns begin_ad 1 REG LC50 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC50; Fanout = 16; REG Node = 'begin_ad'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { begin_ad } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 21.000 ns begin_ad 2 REG LC50 16 " "Info: 2: + IC(2.000 ns) + CELL(19.000 ns) = 21.000 ns; Loc. = LC50; Fanout = 16; REG Node = 'begin_ad'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { begin_ad begin_ad } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "19.000 ns 90.48 % " "Info: Total cell delay = 19.000 ns ( 90.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 9.52 % " "Info: Total interconnect delay = 2.000 ns ( 9.52 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { begin_ad begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "21.000 ns" { begin_ad begin_ad } { 0.0ns 2.0ns } { 0.0ns 19.0ns } } }  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "3.000 ns - Smallest register register " "Info: - Smallest register to register requirement is 3.000 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 0.000 ns " "Info: + Latch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination wr 125.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"wr\" is 125.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source wr 125.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"wr\" is 125.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr destination 23.000 ns + Longest register " "Info: + Longest clock path from clock \"wr\" to destination register is 23.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns wr 1 CLK PIN_67 35 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_67; Fanout = 35; CLK Node = 'wr'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { wr } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 23.000 ns begin_ad 2 REG LC50 16 " "Info: 2: + IC(2.000 ns) + CELL(19.000 ns) = 23.000 ns; Loc. = LC50; Fanout = 16; REG Node = 'begin_ad'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 91.30 % " "Info: Total cell delay = 21.000 ns ( 91.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.70 % " "Info: Total interconnect delay = 2.000 ns ( 8.70 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.0ns 0.0ns 2.0ns } { 0.0ns 2.0ns 19.0ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr source 23.000 ns - Shortest register " "Info: - Shortest clock path from clock \"wr\" to source register is 23.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns wr 1 CLK PIN_67 35 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_67; Fanout = 35; CLK Node = 'wr'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { wr } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 23.000 ns begin_ad 2 REG LC50 16 " "Info: 2: + IC(2.000 ns) + CELL(19.000 ns) = 23.000 ns; Loc. = LC50; Fanout = 16; REG Node = 'begin_ad'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 91.30 % " "Info: Total cell delay = 21.000 ns ( 91.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.70 % " "Info: Total interconnect delay = 2.000 ns ( 8.70 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.0ns 0.0ns 2.0ns } { 0.0ns 2.0ns 19.0ns } } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.0ns 0.0ns 2.0ns } { 0.0ns 2.0ns 19.0ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.0ns 0.0ns 2.0ns } { 0.0ns 2.0ns 19.0ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "4.000 ns + " "Info: + Micro hold delay of destination is 4.000 ns" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.0ns 0.0ns 2.0ns } { 0.0ns 2.0ns 19.0ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.0ns 0.0ns 2.0ns } { 0.0ns 2.0ns 19.0ns } } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { begin_ad begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "21.000 ns" { begin_ad begin_ad } { 0.0ns 2.0ns } { 0.0ns 19.0ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.0ns 0.0ns 2.0ns } { 0.0ns 2.0ns 19.0ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.0ns 0.0ns 2.0ns } { 0.0ns 2.0ns 19.0ns } } }  } 0}
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