xkcon.tan.qmsg

用VHDL语言写的程序实例

{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "clk2mhz " "Info: Detected ripple clock \"clk2mhz\" as buffer" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 58 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk2mhz" } } } }  } 0} { "Info" "ITAN_RIPPLE_CLK" "clk200khz " "Info: Detected ripple clock \"clk200khz\" as buffer" {  } { { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk200khz" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "clk8mhz register lpm_counter:count_rtl_1\|dffs\[5\] register pwm_pina~reg0 56.0 ns " "Info: Slack time is 56.0 ns for clock \"clk8mhz\" between source register \"lpm_counter:count_rtl_1\|dffs\[5\]\" and destination register \"pwm_pina~reg0\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "14.49 MHz 69.0 ns " "Info: Fmax is 14.49 MHz (period= 69.0 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "120.000 ns + Largest register register " "Info: + Largest register to register requirement is 120.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "125.000 ns + " "Info: + Setup relationship between source and destination is 125.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 187.500 ns " "Info: + Latch edge is 187.500 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination clk8mhz 125.000 ns 62.500 ns , Inverted 50 " "Info: Clock period of Destination clock \"clk8mhz\" is 125.000 ns with , Inverted offset of 62.500 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 62.500 ns " "Info: - Launch edge is 62.500 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source clk8mhz 125.000 ns 62.500 ns , Inverted 50 " "Info: Clock period of Source clock \"clk8mhz\" is 125.000 ns with , Inverted offset of 62.500 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk8mhz destination 25.000 ns + Shortest register " "Info: + Shortest clock path from clock \"clk8mhz\" to destination register is 25.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk8mhz 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk8mhz'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { clk8mhz } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns clk2mhz 2 REG LC126 26 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC126; Fanout = 26; REG Node = 'clk2mhz'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "1.000 ns" { clk8mhz clk2mhz } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 25.000 ns pwm_pina~reg0 3 REG LC45 2 " "Info: 3: + IC(2.000 ns) + CELL(19.000 ns) = 25.000 ns; Loc. = LC45; Fanout = 2; REG Node = 'pwm_pina~reg0'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { clk2mhz pwm_pina~reg0 } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 219 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.000 ns 92.00 % " "Info: Total cell delay = 23.000 ns ( 92.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.00 % " "Info: Total interconnect delay = 2.000 ns ( 8.00 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk2mhz pwm_pina~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk2mhz pwm_pina~reg0 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 19.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk8mhz source 25.000 ns - Longest register " "Info: - Longest clock path from clock \"clk8mhz\" to source register is 25.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(3.000 ns) 3.000 ns clk8mhz 1 CLK PIN_83 6 " "Info: 1: + IC(0.000 ns) + CELL(3.000 ns) = 3.000 ns; Loc. = PIN_83; Fanout = 6; CLK Node = 'clk8mhz'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { clk8mhz } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 27 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.000 ns) 4.000 ns clk2mhz 2 REG LC126 26 " "Info: 2: + IC(0.000 ns) + CELL(1.000 ns) = 4.000 ns; Loc. = LC126; Fanout = 26; REG Node = 'clk2mhz'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "1.000 ns" { clk8mhz clk2mhz } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 58 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 25.000 ns lpm_counter:count_rtl_1\|dffs\[5\] 3 REG LC122 9 " "Info: 3: + IC(2.000 ns) + CELL(19.000 ns) = 25.000 ns; Loc. = LC122; Fanout = 9; REG Node = 'lpm_counter:count_rtl_1\|dffs\[5\]'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { clk2mhz lpm_counter:count_rtl_1|dffs[5] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "23.000 ns 92.00 % " "Info: Total cell delay = 23.000 ns ( 92.00 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.00 % " "Info: Total interconnect delay = 2.000 ns ( 8.00 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk2mhz lpm_counter:count_rtl_1|dffs[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk2mhz lpm_counter:count_rtl_1|dffs[5] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 19.000ns } } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk2mhz pwm_pina~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk2mhz pwm_pina~reg0 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 19.000ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk2mhz lpm_counter:count_rtl_1|dffs[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk2mhz lpm_counter:count_rtl_1|dffs[5] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 19.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns - " "Info: - Micro setup delay of destination is 4.000 ns" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 219 -1 0 } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk2mhz pwm_pina~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk2mhz pwm_pina~reg0 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 19.000ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk2mhz lpm_counter:count_rtl_1|dffs[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk2mhz lpm_counter:count_rtl_1|dffs[5] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 19.000ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "64.000 ns - Longest register register " "Info: - Longest register to register delay is 64.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:count_rtl_1\|dffs\[5\] 1 REG LC122 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC122; Fanout = 9; REG Node = 'lpm_counter:count_rtl_1\|dffs\[5\]'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { lpm_counter:count_rtl_1|dffs[5] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "c:/altera/quartus50/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(21.000 ns) 23.000 ns LessThan~656 2 COMB SEXP105 5 " "Info: 2: + IC(2.000 ns) + CELL(21.000 ns) = 23.000 ns; Loc. = SEXP105; Fanout = 5; COMB Node = 'LessThan~656'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { lpm_counter:count_rtl_1|dffs[5] LessThan~656 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(20.000 ns) 43.000 ns LessThan~666 3 COMB LC112 1 " "Info: 3: + IC(0.000 ns) + CELL(20.000 ns) = 43.000 ns; Loc. = LC112; Fanout = 1; COMB Node = 'LessThan~666'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "20.000 ns" { LessThan~656 LessThan~666 } "NODE_NAME" } "" } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 64.000 ns pwm_pina~reg0 4 REG LC45 2 " "Info: 4: + IC(2.000 ns) + CELL(19.000 ns) = 64.000 ns; Loc. = LC45; Fanout = 2; REG Node = 'pwm_pina~reg0'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { LessThan~666 pwm_pina~reg0 } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 219 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "60.000 ns 93.75 % " "Info: Total cell delay = 60.000 ns ( 93.75 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.000 ns 6.25 % " "Info: Total interconnect delay = 4.000 ns ( 6.25 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "64.000 ns" { lpm_counter:count_rtl_1|dffs[5] LessThan~656 LessThan~666 pwm_pina~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "64.000 ns" { lpm_counter:count_rtl_1|dffs[5] LessThan~656 LessThan~666 pwm_pina~reg0 } { 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 21.000ns 20.000ns 19.000ns } } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk2mhz pwm_pina~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk2mhz pwm_pina~reg0 } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 19.000ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "25.000 ns" { clk8mhz clk2mhz lpm_counter:count_rtl_1|dffs[5] } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "25.000 ns" { clk8mhz clk8mhz~out clk2mhz lpm_counter:count_rtl_1|dffs[5] } { 0.000ns 0.000ns 0.000ns 2.000ns } { 0.000ns 3.000ns 1.000ns 19.000ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "64.000 ns" { lpm_counter:count_rtl_1|dffs[5] LessThan~656 LessThan~666 pwm_pina~reg0 } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "64.000 ns" { lpm_counter:count_rtl_1|dffs[5] LessThan~656 LessThan~666 pwm_pina~reg0 } { 0.000ns 2.000ns 0.000ns 2.000ns } { 0.000ns 21.000ns 20.000ns 19.000ns } } }  } 0}
{ "Info" "ITDB_FULL_SLACK_RESULT" "wr register begin_ad register begin_ad 99.0 ns " "Info: Slack time is 99.0 ns for clock \"wr\" between source register \"begin_ad\" and destination register \"begin_ad\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "38.46 MHz 26.0 ns " "Info: Fmax is 38.46 MHz (period= 26.0 ns)" {  } {  } 0} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "120.000 ns + Largest register register " "Info: + Largest register to register requirement is 120.000 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "125.000 ns + " "Info: + Setup relationship between source and destination is 125.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 125.000 ns " "Info: + Latch edge is 125.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination wr 125.000 ns 0.000 ns  50 " "Info: Clock period of Destination clock \"wr\" is 125.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" {  } {  } 0}  } {  } 0} { "Info" "ITDB_EDGE_RESULT" "- Launch 0.000 ns " "Info: - Launch edge is 0.000 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source wr 125.000 ns 0.000 ns  50 " "Info: Clock period of Source clock \"wr\" is 125.000 ns with  offset of 0.000 ns and duty cycle of 50" {  } {  } 0} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" {  } {  } 0}  } {  } 0}  } {  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Largest " "Info: + Largest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr destination 23.000 ns + Shortest register " "Info: + Shortest clock path from clock \"wr\" to destination register is 23.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns wr 1 CLK PIN_67 35 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_67; Fanout = 35; CLK Node = 'wr'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { wr } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 23.000 ns begin_ad 2 REG LC50 16 " "Info: 2: + IC(2.000 ns) + CELL(19.000 ns) = 23.000 ns; Loc. = LC50; Fanout = 16; REG Node = 'begin_ad'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 91.30 % " "Info: Total cell delay = 21.000 ns ( 91.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.70 % " "Info: Total interconnect delay = 2.000 ns ( 8.70 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 19.000ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "wr source 23.000 ns - Longest register " "Info: - Longest clock path from clock \"wr\" to source register is 23.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(2.000 ns) 2.000 ns wr 1 CLK PIN_67 35 " "Info: 1: + IC(0.000 ns) + CELL(2.000 ns) = 2.000 ns; Loc. = PIN_67; Fanout = 35; CLK Node = 'wr'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { wr } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 30 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 23.000 ns begin_ad 2 REG LC50 16 " "Info: 2: + IC(2.000 ns) + CELL(19.000 ns) = 23.000 ns; Loc. = LC50; Fanout = 16; REG Node = 'begin_ad'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "21.000 ns 91.30 % " "Info: Total cell delay = 21.000 ns ( 91.30 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 8.70 % " "Info: Total interconnect delay = 2.000 ns ( 8.70 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 19.000ns } } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 19.000ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 19.000ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.000 ns - " "Info: - Micro clock to output delay of source is 1.000 ns" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "4.000 ns - " "Info: - Micro setup delay of destination is 4.000 ns" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 19.000ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 19.000ns } } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "21.000 ns - Longest register register " "Info: - Longest register to register delay is 21.000 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns begin_ad 1 REG LC50 16 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC50; Fanout = 16; REG Node = 'begin_ad'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "" { begin_ad } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.000 ns) + CELL(19.000 ns) 21.000 ns begin_ad 2 REG LC50 16 " "Info: 2: + IC(2.000 ns) + CELL(19.000 ns) = 21.000 ns; Loc. = LC50; Fanout = 16; REG Node = 'begin_ad'" {  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { begin_ad begin_ad } "NODE_NAME" } "" } } { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 60 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "19.000 ns 90.48 % " "Info: Total cell delay = 19.000 ns ( 90.48 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.000 ns 9.52 % " "Info: Total interconnect delay = 2.000 ns ( 9.52 % )" {  } {  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { begin_ad begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "21.000 ns" { begin_ad begin_ad } { 0.000ns 2.000ns } { 0.000ns 19.000ns } } }  } 0}  } { { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 19.000ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "23.000 ns" { wr begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "23.000 ns" { wr wr~out begin_ad } { 0.000ns 0.000ns 2.000ns } { 0.000ns 2.000ns 19.000ns } } } { "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" "" { Report "D:/文档/相控改造/程序代码/CPLD/db/xkcon_cmp.qrpt" Compiler "xkcon" "UNKNOWN" "V1" "D:/文档/相控改造/程序代码/CPLD/db/xkcon.quartus_db" { Floorplan "D:/文档/相控改造/程序代码/CPLD/" "" "21.000 ns" { begin_ad begin_ad } "NODE_NAME" } "" } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "21.000 ns" { begin_ad begin_ad } { 0.000ns 2.000ns } { 0.000ns 19.000ns } } }  } 0}