xkcon.tan.qmsg

用VHDL语言写的程序实例

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk8mhz " "Info: Assuming node \"clk8mhz\" is an undefined clock" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 27 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clk8mhz" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "wr " "Info: Assuming node \"wr\" is an undefined clock" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 30 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "wr" } } } }  } 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "ale " "Info: Assuming node \"ale\" is an undefined clock" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 28 -1 0 } } { "c:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "c:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "ale" } } } }  } 0}  } {  } 0}