xkcon.drc.qmsg

用VHDL语言写的程序实例

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Design Assistant Quartus II " "Info: Running Quartus II Design Assistant" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 148 04/26/2005 SJ Full Version " "Info: Version 5.0 Build 148 04/26/2005 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat Nov 12 16:53:53 2005 " "Info: Processing started: Sat Nov 12 16:53:53 2005" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_drc --read_settings_files=on --write_settings_files=off xkcon -c xkcon " "Info: Command: quartus_drc --read_settings_files=on --write_settings_files=off xkcon -c xkcon" {  } {  } 0}
{ "Critical Warning" "WDRC_CLOCK_SPINES" "Clock signal should be a global signal 4 " "Critical Warning: Design Assistant warning: Clock signal should be a global signal. Found 4 node(s) related to this rule." { { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " clk200khz " "Critical Warning: Node  \"clk200khz\"" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 39 -1 0 } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { clk200khz } {  } {  } } } { "c:/altera/quartus50/bin/RTL_Viewer.qrui" "" { "RTL Viewer" "c:/altera/quartus50/bin/RTL_Viewer.qrui" { clk200khz } } }  } 1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " clk2mhz " "Critical Warning: Node  \"clk2mhz\"" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 38 -1 0 } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { clk2mhz } {  } {  } } } { "c:/altera/quartus50/bin/RTL_Viewer.qrui" "" { "RTL Viewer" "c:/altera/quartus50/bin/RTL_Viewer.qrui" { clk2mhz } } }  } 1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " wr " "Critical Warning: Node  \"wr\"" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 10 -1 0 } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { wr } {  } {  } } } { "c:/altera/quartus50/bin/RTL_Viewer.qrui" "" { "RTL Viewer" "c:/altera/quartus50/bin/RTL_Viewer.qrui" { wr } } }  } 1} { "Critical Warning" "WDRC_NODES_CRITICAL_WARNING" " ale " "Critical Warning: Node  \"ale\"" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 8 -1 0 } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { ale } {  } {  } } } { "c:/altera/quartus50/bin/RTL_Viewer.qrui" "" { "RTL Viewer" "c:/altera/quartus50/bin/RTL_Viewer.qrui" { ale } } }  } 1}  } {  } 1}
{ "Warning" "WDRC_ILLEGAL_CLOCK_NET" "Clock signal source should drive only input clock ports 2 " "Warning: Design Assistant warning: Clock signal source should drive only input clock ports. Found 2 nodes related to this rule." { { "Warning" "WDRC_NODES_WARNING" " clk200khz " "Warning: Node  \"clk200khz\"" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 39 -1 0 } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { clk200khz } {  } {  } } } { "c:/altera/quartus50/bin/RTL_Viewer.qrui" "" { "RTL Viewer" "c:/altera/quartus50/bin/RTL_Viewer.qrui" { clk200khz } } }  } 0} { "Warning" "WDRC_NODES_WARNING" " clk2mhz " "Warning: Node  \"clk2mhz\"" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 38 -1 0 } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { clk2mhz } {  } {  } } } { "c:/altera/quartus50/bin/RTL_Viewer.qrui" "" { "RTL Viewer" "c:/altera/quartus50/bin/RTL_Viewer.qrui" { clk2mhz } } }  } 0}  } {  } 0}
{ "Warning" "WDRC_MIXED_CLK_EDGE" "Clock signal source should not drive registers that are triggered by different clock edges 1 " "Warning: Design Assistant warning: Clock signal source should not drive registers that are triggered by different clock edges. Found 1 node(s) related to this rule." { { "Warning" "WDRC_NODES_WARNING" " clk2mhz " "Warning: Node  \"clk2mhz\"" {  } { { "xkcon.vhd" "" { Text "D:/文档/相控改造/程序代码/CPLD/xkcon.vhd" 38 -1 0 } } { "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "c:/altera/quartus50/bin/Technology_Viewer.qrui" "" { clk2mhz } {  } {  } } } { "c:/altera/quartus50/bin/RTL_Viewer.qrui" "" { "RTL Viewer" "c:/altera/quartus50/bin/RTL_Viewer.qrui" { clk2mhz } } }  } 0}  } {  } 0}