at91sam9260_dma.html

AT91SAM 系列微控制器的NAND Flash支持代码 描述怎样将NAND Flash和AT91SAM 系列微控制器连接起来。

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<a name="DMA_DSR1"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_DSR1  <i>Destination Scatter Register for channel 1</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_DSR1">AT91C_DMA_DSR1</a></i> 0x008000A8</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">19..0</td><td align="CENTER"><a name="DMA_DSI"></a><b>DMA_DSI</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DSI">AT91C_DMA_DSI</a></font></td><td><b>Destination Scatter Interval</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..20</td><td align="CENTER"><a name="DMA_DSC"></a><b>DMA_DSC</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DSC">AT91C_DMA_DSC</a></font></td><td><b>Destination Scatter Count</b></td></tr>
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<a name="DMA_RAWTFR"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_RAWTFR  <i>Raw Status for IntTfr Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_RAWTFR">AT91C_DMA_RAWTFR</a></i> 0x008002C0</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_RAW"></a><b>DMA_RAW</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_RAW">AT91C_DMA_RAW</a></font></td><td><b>Raw Interrupt for each Channel</b></td></tr>
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<a name="DMA_RAWBLOCK"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_RAWBLOCK  <i>Raw Status for IntBlock Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_RAWBLOCK">AT91C_DMA_RAWBLOCK</a></i> 0x008002C8</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_RAW"></a><b>DMA_RAW</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_RAW">AT91C_DMA_RAW</a></font></td><td><b>Raw Interrupt for each Channel</b></td></tr>
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<a name="DMA_RAWSRCTRAN"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_RAWSRCTRAN  <i>Raw Status for IntSrcTran Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_RAWSRCTRAN">AT91C_DMA_RAWSRCTRAN</a></i> 0x008002D0</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_RAW"></a><b>DMA_RAW</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_RAW">AT91C_DMA_RAW</a></font></td><td><b>Raw Interrupt for each Channel</b></td></tr>
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<a name="DMA_RAWDSTTRAN"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_RAWDSTTRAN  <i>Raw Status for IntDstTran Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_RAWDSTTRAN">AT91C_DMA_RAWDSTTRAN</a></i> 0x008002D8</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_RAW"></a><b>DMA_RAW</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_RAW">AT91C_DMA_RAW</a></font></td><td><b>Raw Interrupt for each Channel</b></td></tr>
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<a name="DMA_RAWERR"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_RAWERR  <i>Raw Status for IntErr Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_RAWERR">AT91C_DMA_RAWERR</a></i> 0x008002E0</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_RAW"></a><b>DMA_RAW</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_RAW">AT91C_DMA_RAW</a></font></td><td><b>Raw Interrupt for each Channel</b></td></tr>
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<a name="DMA_STATUSTFR"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_STATUSTFR  <i>Status for IntTfr Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_STATUSTFR">AT91C_DMA_STATUSTFR</a></i> 0x008002E8</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_STATUS"></a><b>DMA_STATUS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_STATUS">AT91C_DMA_STATUS</a></font></td><td><b>Interrupt for each Channel</b></td></tr>
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<a name="DMA_STATUSBLOCK"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_STATUSBLOCK  <i>Status for IntBlock Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_STATUSBLOCK">AT91C_DMA_STATUSBLOCK</a></i> 0x008002F0</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_STATUS"></a><b>DMA_STATUS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_STATUS">AT91C_DMA_STATUS</a></font></td><td><b>Interrupt for each Channel</b></td></tr>
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<a name="DMA_STATUSSRCTRAN"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_STATUSSRCTRAN  <i>Status for IntSrcTran Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_STATUSSRCTRAN">AT91C_DMA_STATUSSRCTRAN</a></i> 0x008002F8</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_STATUS"></a><b>DMA_STATUS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_STATUS">AT91C_DMA_STATUS</a></font></td><td><b>Interrupt for each Channel</b></td></tr>
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<a name="DMA_STATUSDSTTRAN"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_STATUSDSTTRAN  <i>Status for IntDstTran IInterrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_STATUSDSTTRAN">AT91C_DMA_STATUSDSTTRAN</a></i> 0x00800300</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_STATUS"></a><b>DMA_STATUS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_STATUS">AT91C_DMA_STATUS</a></font></td><td><b>Interrupt for each Channel</b></td></tr>
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<a name="DMA_STATUSERR"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_STATUSERR  <i>Status for IntErr IInterrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_STATUSERR">AT91C_DMA_STATUSERR</a></i> 0x00800308</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_RAW"></a><b>DMA_RAW</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_RAW">AT91C_DMA_RAW</a></font></td><td><b>Raw Interrupt for each Channel</b></td></tr>
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<a name="DMA_MASKTFR"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_MASKTFR  <i>Mask for IntTfr Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_MASKTFR">AT91C_DMA_MASKTFR</a></i> 0x00800310</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_INT_MASK"></a><b>DMA_INT_MASK</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_MASK">AT91C_DMA_INT_MASK</a></font></td><td><b>Interrupt Mask for each Channel</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10..8</td><td align="CENTER"><a name="DMA_INT_M_WE"></a><b>DMA_INT_M_WE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_M_WE">AT91C_DMA_INT_M_WE</a></font></td><td><b>Interrupt Mask Write Enable for each Channel</b></td></tr>
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<a name="DMA_MASKBLOCK"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_MASKBLOCK  <i>Mask for IntBlock Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_MASKBLOCK">AT91C_DMA_MASKBLOCK</a></i> 0x00800318</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_INT_MASK"></a><b>DMA_INT_MASK</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_MASK">AT91C_DMA_INT_MASK</a></font></td><td><b>Interrupt Mask for each Channel</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10..8</td><td align="CENTER"><a name="DMA_INT_M_WE"></a><b>DMA_INT_M_WE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_M_WE">AT91C_DMA_INT_M_WE</a></font></td><td><b>Interrupt Mask Write Enable for each Channel</b></td></tr>
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<a name="DMA_MASKSRCTRAN"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_MASKSRCTRAN  <i>Mask for IntSrcTran Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_MASKSRCTRAN">AT91C_DMA_MASKSRCTRAN</a></i> 0x00800320</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_INT_MASK"></a><b>DMA_INT_MASK</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_MASK">AT91C_DMA_INT_MASK</a></font></td><td><b>Interrupt Mask for each Channel</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10..8</td><td align="CENTER"><a name="DMA_INT_M_WE"></a><b>DMA_INT_M_WE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_M_WE">AT91C_DMA_INT_M_WE</a></font></td><td><b>Interrupt Mask Write Enable for each Channel</b></td></tr>
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<a name="DMA_MASKDSTTRAN"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_MASKDSTTRAN  <i>Mask for IntDstTran Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_MASKDSTTRAN">AT91C_DMA_MASKDSTTRAN</a></i> 0x00800328</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_INT_MASK"></a><b>DMA_INT_MASK</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_MASK">AT91C_DMA_INT_MASK</a></font></td><td><b>Interrupt Mask for each Channel</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10..8</td><td align="CENTER"><a name="DMA_INT_M_WE"></a><b>DMA_INT_M_WE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_M_WE">AT91C_DMA_INT_M_WE</a></font></td><td><b>Interrupt Mask Write Enable for each Channel</b></td></tr>
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<a name="DMA_MASKERR"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_MASKERR  <i>Mask for IntErr Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_MASKERR">AT91C_DMA_MASKERR</a></i> 0x00800330</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td align="CENTER"><a name="DMA_INT_MASK"></a><b>DMA_INT_MASK</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_MASK">AT91C_DMA_INT_MASK</a></font></td><td><b>Interrupt Mask for each Channel</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10..8</td><td align="CENTER"><a name="DMA_INT_M_WE"></a><b>DMA_INT_M_WE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_M_WE">AT91C_DMA_INT_M_WE</a></font></td><td><b>Interrupt Mask Write Enable for each Channel</b></td></tr>
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<a name="DMA_CLEARTFR"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_CLEARTFR  <i>Clear for IntTfr Interrupt</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_CLEARTFR">AT91C_DMA_CLEARTFR</a></i> 0x00800338</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">2..0</td><td al