at91sam9260_dma.html

AT91SAM 系列微控制器的NAND Flash支持代码 描述怎样将NAND Flash和AT91SAM 系列微控制器连接起来。

<a name="DMA_CTL1l"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_CTL1l  <i>Control Register for channel 1 - low</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_CTL1l">AT91C_DMA_CTL1l</a></i> 0x00800070</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="DMA_INT_EN"></a><b>DMA_INT_EN</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_EN">AT91C_DMA_INT_EN</a></font></td><td><b>Interrupt Enable Bit</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3..1</td><td align="CENTER"><a name="DMA_DST_TR_WIDTH"></a><b>DMA_DST_TR_WIDTH</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DST_TR_WIDTH">AT91C_DMA_DST_TR_WIDTH</a></font></td><td><b>Destination Transfer Width</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6..4</td><td align="CENTER"><a name="DMA_SRC_TR_WIDTH"></a><b>DMA_SRC_TR_WIDTH</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SRC_TR_WIDTH">AT91C_DMA_SRC_TR_WIDTH</a></font></td><td><b>Source Transfer Width</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8..7</td><td align="CENTER"><a name="DMA_DINC"></a><b>DMA_DINC</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DINC">AT91C_DMA_DINC</a></font></td><td><b>Destination Address Increment</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10..9</td><td align="CENTER"><a name="DMA_SINC"></a><b>DMA_SINC</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SINC">AT91C_DMA_SINC</a></font></td><td><b>Source Address Increment</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13..11</td><td align="CENTER"><a name="DMA_DEST_MSIZE"></a><b>DMA_DEST_MSIZE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DEST_MSIZE">AT91C_DMA_DEST_MSIZE</a></font></td><td><b>Destination Burst Transaction Length</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16..14</td><td align="CENTER"><a name="DMA_SRC_MSIZE"></a><b>DMA_SRC_MSIZE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SRC_MSIZE">AT91C_DMA_SRC_MSIZE</a></font></td><td><b>Source Burst Transaction Length</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="DMA_S_GATH_EN"></a><b>DMA_S_GATH_EN</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_S_GATH_EN">AT91C_DMA_S_GATH_EN</a></font></td><td><b>Source Gather Enable Bit</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="DMA_D_SCAT_EN"></a><b>DMA_D_SCAT_EN</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_D_SCAT_EN">AT91C_DMA_D_SCAT_EN</a></font></td><td><b>Destination Scatter Enable Bit</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22..20</td><td align="CENTER"><a name="DMA_TT_FC"></a><b>DMA_TT_FC</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_TT_FC">AT91C_DMA_TT_FC</a></font></td><td><b>Transfer Type and Flow Control</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">24..23</td><td align="CENTER"><a name="DMA_DMS"></a><b>DMA_DMS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DMS">AT91C_DMA_DMS</a></font></td><td><b>Destination Master Select</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">26..25</td><td align="CENTER"><a name="DMA_SMS"></a><b>DMA_SMS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SMS">AT91C_DMA_SMS</a></font></td><td><b>Source Master Select</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">27</td><td align="CENTER"><a name="DMA_LLP_D_EN"></a><b>DMA_LLP_D_EN</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_LLP_D_EN">AT91C_DMA_LLP_D_EN</a></font></td><td><b>Destination Block Chaining Enable</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">28</td><td align="CENTER"><a name="DMA_LLP_S_EN"></a><b>DMA_LLP_S_EN</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_LLP_S_EN">AT91C_DMA_LLP_S_EN</a></font></td><td><b>Source Block Chaining Enable</b></td></tr>
</null></table>
<a name="DMA_CTL1h"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_CTL1h  <i>Control Register for channel 1 - high</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_CTL1h">AT91C_DMA_CTL1h</a></i> 0x00800074</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">11..0</td><td align="CENTER"><a name="DMA_BLOCK_TS"></a><b>DMA_BLOCK_TS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_BLOCK_TS">AT91C_DMA_BLOCK_TS</a></font></td><td><b>Block Transfer Size</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">12</td><td align="CENTER"><a name="DMA_DONE"></a><b>DMA_DONE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DONE">AT91C_DMA_DONE</a></font></td><td><b>Done bit</b></td></tr>
</null></table>
<a name="DMA_SSTAT1"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_SSTAT1  <i>Source Status Register for channel 1</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_SSTAT1">AT91C_DMA_SSTAT1</a></i> 0x00800078</font></null></ul><br>Source Status Information<a name="DMA_DSTAT1"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_DSTAT1  <i>Destination Status Register for channel 1</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_DSTAT1">AT91C_DMA_DSTAT1</a></i> 0x00800080</font></null></ul><br>Destination Status Information<a name="DMA_SSTATAR1"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_SSTATAR1  <i>Source Status Adress Register for channel 1</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_SSTATAR1">AT91C_DMA_SSTATAR1</a></i> 0x00800088</font></null></ul><br>Source Status Information Address<a name="DMA_DSTATAR1"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_DSTATAR1  <i>Destination Status Adress Register for channel 1</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_DSTATAR1">AT91C_DMA_DSTATAR1</a></i> 0x00800090</font></null></ul><br>Destination Status Information Address<a name="DMA_CFG1l"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_CFG1l  <i>Configuration Register for channel 1 - low</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_CFG1l">AT91C_DMA_CFG1l</a></i> 0x00800098</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..5</td><td align="CENTER"><a name="DMA_CH_PRIOR"></a><b>DMA_CH_PRIOR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_CH_PRIOR">AT91C_DMA_CH_PRIOR</a></font></td><td><b>Channel Priority</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="DMA_CH_SUSP"></a><b>DMA_CH_SUSP</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_CH_SUSP">AT91C_DMA_CH_SUSP</a></font></td><td><b>Channel Suspend</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="DMA_FIFO_EMPT"></a><b>DMA_FIFO_EMPT</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_FIFO_EMPT">AT91C_DMA_FIFO_EMPT</a></font></td><td><b>Fifo Empty</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="DMA_HS_SEL_DS"></a><b>DMA_HS_SEL_DS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_HS_SEL_DS">AT91C_DMA_HS_SEL_DS</a></font></td><td><b>Destination Software or Hardware Handshaking Select</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="DMA_HS_SEL_SR"></a><b>DMA_HS_SEL_SR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_HS_SEL_SR">AT91C_DMA_HS_SEL_SR</a></font></td><td><b>Source Software or Hardware Handshaking Select</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13..12</td><td align="CENTER"><a name="DMA_LOCK_CH_L"></a><b>DMA_LOCK_CH_L</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_LOCK_CH_L">AT91C_DMA_LOCK_CH_L</a></font></td><td><b>Channel Lock Level</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="DMA_LOCK_B_L"></a><b>DMA_LOCK_B_L</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_LOCK_B_L">AT91C_DMA_LOCK_B_L</a></font></td><td><b>Bus Lock Level</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="DMA_LOCK_CH"></a><b>DMA_LOCK_CH</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_LOCK_CH">AT91C_DMA_LOCK_CH</a></font></td><td><b>Channel Lock Bit</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="DMA_LOCK_B"></a><b>DMA_LOCK_B</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_LOCK_B">AT91C_DMA_LOCK_B</a></font></td><td><b>Bus Lock Bit</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="DMA_DS_HS_POL"></a><b>DMA_DS_HS_POL</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DS_HS_POL">AT91C_DMA_DS_HS_POL</a></font></td><td><b>Destination Handshaking Interface Polarity</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">19</td><td align="CENTER"><a name="DMA_SR_HS_POL"></a><b>DMA_SR_HS_POL</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SR_HS_POL">AT91C_DMA_SR_HS_POL</a></font></td><td><b>Source Handshaking Interface Polarity</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">29..20</td><td align="CENTER"><a name="DMA_MAX_ABRST"></a><b>DMA_MAX_ABRST</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_MAX_ABRST">AT91C_DMA_MAX_ABRST</a></font></td><td><b>Maximum AMBA Burst Length</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">30</td><td align="CENTER"><a name="DMA_RELOAD_SR"></a><b>DMA_RELOAD_SR</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_RELOAD_SR">AT91C_DMA_RELOAD_SR</a></font></td><td><b>Automatic Source Reload</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31</td><td align="CENTER"><a name="DMA_RELOAD_DS"></a><b>DMA_RELOAD_DS</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_RELOAD_DS">AT91C_DMA_RELOAD_DS</a></font></td><td><b>Automatic Destination Reload</b></td></tr>
</null></table>
<a name="DMA_CFG1h"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_CFG1h  <i>Configuration Register for channel 1 - high</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_CFG1h">AT91C_DMA_CFG1h</a></i> 0x0080009C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="DMA_FCMODE"></a><b>DMA_FCMODE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_FCMODE">AT91C_DMA_FCMODE</a></font></td><td><b>Flow Control Mode</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="DMA_FIFO_MODE"></a><b>DMA_FIFO_MODE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_FIFO_MODE">AT91C_DMA_FIFO_MODE</a></font></td><td><b>Fifo Mode Select</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">4..2</td><td align="CENTER"><a name="DMA_PROTCTL"></a><b>DMA_PROTCTL</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_PROTCTL">AT91C_DMA_PROTCTL</a></font></td><td><b>Protection Control</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">5</td><td align="CENTER"><a name="DMA_DS_UPD_EN"></a><b>DMA_DS_UPD_EN</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DS_UPD_EN">AT91C_DMA_DS_UPD_EN</a></font></td><td><b>Destination Status Update Enable</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="DMA_SS_UPD_EN"></a><b>DMA_SS_UPD_EN</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SS_UPD_EN">AT91C_DMA_SS_UPD_EN</a></font></td><td><b>Source Status Update Enable</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10..7</td><td align="CENTER"><a name="DMA_SRC_PER"></a><b>DMA_SRC_PER</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SRC_PER">AT91C_DMA_SRC_PER</a></font></td><td><b>Source Hardware Handshaking Interface</b><br>Assigns a h/w handshaking interface (0-DMAH_NUM_HS_INT-1) to the source of channel X if CFGx.HS_SEL_DST field is 0</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">14..11</td><td align="CENTER"><a name="DMA_DEST_PER"></a><b>DMA_DEST_PER</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DEST_PER">AT91C_DMA_DEST_PER</a></font></td><td><b>Destination Hardware Handshaking Interface</b></td></tr>
</null></table>
<a name="DMA_SGR1"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_SGR1  <i>Source Gather Register for channel 1</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_SGR1">AT91C_DMA_SGR1</a></i> 0x008000A0</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">19..0</td><td align="CENTER"><a name="DMA_SGI"></a><b>DMA_SGI</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SGI">AT91C_DMA_SGI</a></font></td><td><b>Source Gather Interval</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">31..20</td><td align="CENTER"><a name="DMA_SGC"></a><b>DMA_SGC</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SGC">AT91C_DMA_SGC</a></font></td><td><b>Source Gather Count</b></td></tr>