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<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x2F8</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_STATUSSRCTRAN">DMA_STATUSSRCTRAN</a></font></td><td><font size="-1">Status for IntSrcTran Interrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x300</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_STATUSDSTTRAN">DMA_STATUSDSTTRAN</a></font></td><td><font size="-1">Status for IntDstTran IInterrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x308</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_STATUSERR">DMA_STATUSERR</a></font></td><td><font size="-1">Status for IntErr IInterrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x310</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_MASKTFR">DMA_MASKTFR</a></font></td><td><font size="-1">Mask for IntTfr Interrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x318</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_MASKBLOCK">DMA_MASKBLOCK</a></font></td><td><font size="-1">Mask for IntBlock Interrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x320</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_MASKSRCTRAN">DMA_MASKSRCTRAN</a></font></td><td><font size="-1">Mask for IntSrcTran Interrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x328</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_MASKDSTTRAN">DMA_MASKDSTTRAN</a></font></td><td><font size="-1">Mask for IntDstTran Interrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x330</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_MASKERR">DMA_MASKERR</a></font></td><td><font size="-1">Mask for IntErr Interrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x338</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_CLEARTFR">DMA_CLEARTFR</a></font></td><td><font size="-1">Clear for IntTfr Interrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x340</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_CLEARBLOCK">DMA_CLEARBLOCK</a></font></td><td><font size="-1">Clear for IntBlock Interrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x348</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_CLEARSRCTRAN">DMA_CLEARSRCTRAN</a></font></td><td><font size="-1">Clear for IntSrcTran Interrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x350</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_CLEARDSTTRAN">DMA_CLEARDSTTRAN</a></font></td><td><font size="-1">Clear for IntDstTran IInterrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x358</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_CLEARERR">DMA_CLEARERR</a></font></td><td><font size="-1">Clear for IntErr Interrupt</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x360</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_STATUSINT">DMA_STATUSINT</a></font></td><td><font size="-1">Status for each Interrupt Type</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x368</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_REQSRCREG">DMA_REQSRCREG</a></font></td><td><font size="-1">Source Software Transaction Request Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x370</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_REQDSTREG">DMA_REQDSTREG</a></font></td><td><font size="-1">Destination Software Transaction Request Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x378</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_SGLREQSRCREG">DMA_SGLREQSRCREG</a></font></td><td><font size="-1">Single Source Software Transaction Request Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x380</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_SGLREQDSTREG">DMA_SGLREQDSTREG</a></font></td><td><font size="-1">Single Destination Software Transaction Request Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x388</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_LSTREQSRCREG">DMA_LSTREQSRCREG</a></font></td><td><font size="-1">Last Source Software Transaction Request Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x390</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_LSTREQDSTREG">DMA_LSTREQDSTREG</a></font></td><td><font size="-1">Last Destination Software Transaction Request Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x398</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_DMACFGREG">DMA_DMACFGREG</a></font></td><td><font size="-1">DW_ahb_dmac Configuration Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x3A0</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_CHENREG">DMA_CHENREG</a></font></td><td><font size="-1">DW_ahb_dmac Channel Enable Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x3A8</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_DMAIDREG">DMA_DMAIDREG</a></font></td><td><font size="-1">DW_ahb_dmac ID Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x3B0</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_DMATESTREG">DMA_DMATESTREG</a></font></td><td><font size="-1">DW_ahb_dmac Test Register</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x3B8</b></font></td><td><font size="-1"><a href="AT91SAM9260_DMA.html#DMA_VERSIONID">DMA_VERSIONID</a></font></td><td><font size="-1">DW_ahb_dmac Version ID Register</font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM9260_h.html#AT91F_DMA_Enable">AT91F_DMA_Enable</a></b></font></td><td><font size="-1">Enable the DMA controller</font></td></tr>
</null></table></null><h2>DMA Register Description</h2>
<null><a name="DMA_SAR0"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_SAR0 <i>Source Address Register for channel 0</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_SAR0">AT91C_DMA_SAR0</a></i> 0x00800000</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">31..0</td><td align="CENTER"><a name="DMA_SADD"></a><b>DMA_SADD</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SADD">AT91C_DMA_SADD</a></font></td><td><b>Source Address of DMA Transfer</b></td></tr>
</null></table>
<a name="DMA_DAR0"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_DAR0 <i>Destination Address Register for channel 0</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_DAR0">AT91C_DMA_DAR0</a></i> 0x00800008</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">31..0</td><td align="CENTER"><a name="DMA_DADD"></a><b>DMA_DADD</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DADD">AT91C_DMA_DADD</a></font></td><td><b>Destination Address of DMA Transfer</b></td></tr>
</null></table>
<a name="DMA_LLP0"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_LLP0 <i>Linked List Pointer Register for channel 0</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_LLP0">AT91C_DMA_LLP0</a></i> 0x00800010</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">31..0</td><td align="CENTER"><a name="DMA_LOC"></a><b>DMA_LOC</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_LOC">AT91C_DMA_LOC</a></font></td><td><b>Address of the Next LLI</b></td></tr>
</null></table>
<a name="DMA_CTL0l"></a><h4><a href="#DMA">DMA</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> DMA_CTL0l <i>Control Register for channel 0 - low</i></h4><ul><null><font size="-2"><li><b>DMA</b> <i><a href="AT91SAM9260_h.html#AT91C_DMA_CTL0l">AT91C_DMA_CTL0l</a></i> 0x00800018</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="DMA_INT_EN"></a><b>DMA_INT_EN</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_INT_EN">AT91C_DMA_INT_EN</a></font></td><td><b>Interrupt Enable Bit</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">3..1</td><td align="CENTER"><a name="DMA_DST_TR_WIDTH"></a><b>DMA_DST_TR_WIDTH</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DST_TR_WIDTH">AT91C_DMA_DST_TR_WIDTH</a></font></td><td><b>Destination Transfer Width</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6..4</td><td align="CENTER"><a name="DMA_SRC_TR_WIDTH"></a><b>DMA_SRC_TR_WIDTH</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SRC_TR_WIDTH">AT91C_DMA_SRC_TR_WIDTH</a></font></td><td><b>Source Transfer Width</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8..7</td><td align="CENTER"><a name="DMA_DINC"></a><b>DMA_DINC</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DINC">AT91C_DMA_DINC</a></font></td><td><b>Destination Address Increment</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10..9</td><td align="CENTER"><a name="DMA_SINC"></a><b>DMA_SINC</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SINC">AT91C_DMA_SINC</a></font></td><td><b>Source Address Increment</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13..11</td><td align="CENTER"><a name="DMA_DEST_MSIZE"></a><b>DMA_DEST_MSIZE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_DEST_MSIZE">AT91C_DMA_DEST_MSIZE</a></font></td><td><b>Destination Burst Transaction Length</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16..14</td><td align="CENTER"><a name="DMA_SRC_MSIZE"></a><b>DMA_SRC_MSIZE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_SRC_MSIZE">AT91C_DMA_SRC_MSIZE</a></font></td><td><b>Source Burst Transaction Length</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="DMA_S_GATH_EN"></a><b>DMA_S_GATH_EN</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_S_GATH_EN">AT91C_DMA_S_GATH_EN</a></font></td><td><b>Source Gather Enable Bit</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">18</td><td align="CENTER"><a name="DMA_D_SCAT_EN"></a><b>DMA_D_SCAT_EN</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_D_SCAT_EN">AT91C_DMA_D_SCAT_EN</a></font></td><td><b>Destination Scatter Enable Bit</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">22..20</td><td align="CENTER"><a name="DMA_TT_FC"></a><b>DMA_TT_FC</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_DMA_TT_FC">AT91C_DMA_TT_FC</a></font></td><td><b>Transfer Type and Flow Control</b></td></tr>
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