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<h1>AHB Matrix Interface Peripheral</h1>
<null><a name="MATRIX"></a><b>MATRIX</b> <i><font size="-1">(<a href="AT91SAM9260_h.html#AT91S_MATRIX">AT91S_MATRIX</a>)</font></i><b> 0xFFFFEE00 </b><i><font size="-1">(<a href="AT91SAM9260_h.html#AT91C_BASE_MATRIX">AT91C_BASE_MATRIX</a>)</font></i>
<br></null><a name="MATRIX"></a><h2>MATRIX Software API <i><font size="-1">(<a href="AT91SAM9260_h.html#AT91S_MATRIX">AT91S_MATRIX</a>)</font></i></h2>
<a name="MATRIX"></a><null><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Offset</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Field</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x0</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_MCFG0">MATRIX_MCFG0</a></font></td><td><font size="-1"> Master Configuration Register 0 (ram96k) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_MCFG1">MATRIX_MCFG1</a></font></td><td><font size="-1"> Master Configuration Register 1 (rom) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x8</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_MCFG2">MATRIX_MCFG2</a></font></td><td><font size="-1"> Master Configuration Register 2 (hperiphs) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xC</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_MCFG3">MATRIX_MCFG3</a></font></td><td><font size="-1"> Master Configuration Register 3 (ebi)</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x10</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_MCFG4">MATRIX_MCFG4</a></font></td><td><font size="-1"> Master Configuration Register 4 (bridge) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x14</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_MCFG5">MATRIX_MCFG5</a></font></td><td><font size="-1"> Master Configuration Register 5 (mailbox) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x40</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_SCFG0">MATRIX_SCFG0</a></font></td><td><font size="-1"> Slave Configuration Register 0 (ram96k) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x44</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_SCFG1">MATRIX_SCFG1</a></font></td><td><font size="-1"> Slave Configuration Register 1 (rom) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x48</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_SCFG2">MATRIX_SCFG2</a></font></td><td><font size="-1"> Slave Configuration Register 2 (hperiphs) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x4C</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_SCFG3">MATRIX_SCFG3</a></font></td><td><font size="-1"> Slave Configuration Register 3 (ebi)</font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x50</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_SCFG4">MATRIX_SCFG4</a></font></td><td><font size="-1"> Slave Configuration Register 4 (bridge) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x80</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_PRAS0">MATRIX_PRAS0</a></font></td><td><font size="-1"> PRAS0 (ram0) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x88</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_PRAS1">MATRIX_PRAS1</a></font></td><td><font size="-1"> PRAS1 (ram1) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x90</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_PRAS2">MATRIX_PRAS2</a></font></td><td><font size="-1"> PRAS2 (ram2) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x98</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_PRAS3">MATRIX_PRAS3</a></font></td><td><font size="-1"> PRAS3 (ebi) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0xA0</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_PRAS4">MATRIX_PRAS4</a></font></td><td><font size="-1"> PRAS4 (periph) </font></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC"><font size="-1"><b>0x100</b></font></td><td><font size="-1"><a href="AT91SAM9260_MATRIX.html#MATRIX_MRCR">MATRIX_MRCR</a></font></td><td><font size="-1"> Master Remp Control Register </font></td></tr>
</null></table><br><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><font size="-1"><b>Function</b></font></th><th bgcolor="#FFFFCC"><font size="-1"><b>Description</b></font></th><tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="#AT91F_MATRIX_Disable_Remap_ARM-D">AT91F_MATRIX_Disable_Remap_ARM-D</a></b></font></td><td><font size="-1">Disable Remap of ARM-D</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM9260_h.html#AT91F_MATRIX_Disable_Remap_ARM">AT91F_MATRIX_Disable_Remap_ARM</a></b></font></td><td><font size="-1">Disable Remap of ARM</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM9260_h.html#AT91F_MATRIX_Remap_ARMI">AT91F_MATRIX_Remap_ARMI</a></b></font></td><td><font size="-1">Enable Remap of ARM-I</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM9260_h.html#AT91F_MATRIX_Remap_ARM">AT91F_MATRIX_Remap_ARM</a></b></font></td><td><font size="-1">Enable Remap of ARM</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM9260_h.html#AT91F_MATRIX_Disable_Remap_ARMI">AT91F_MATRIX_Disable_Remap_ARMI</a></b></font></td><td><font size="-1">Disable Remap of ARM-I</font></td></tr>
<tr><td bgcolor="#FFFFCC"><font size="-1"><b><a href="lib_AT91SAM9260_h.html#AT91F_MATRIX_Remap_ARMD">AT91F_MATRIX_Remap_ARMD</a></b></font></td><td><font size="-1">Enable Remap of ARM-D</font></td></tr>
</null></table></null><h2>MATRIX Register Description</h2>
<null><a name="MATRIX_MCFG0"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG0 <i> Master Configuration Register 0 (ram96k) </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG0">AT91C_MATRIX_MCFG0</a></i> 0xFFFFEE00</font></null></ul><a name="MATRIX_MCFG1"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG1 <i> Master Configuration Register 1 (rom) </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG1">AT91C_MATRIX_MCFG1</a></i> 0xFFFFEE04</font></null></ul><a name="MATRIX_MCFG2"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG2 <i> Master Configuration Register 2 (hperiphs) </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG2">AT91C_MATRIX_MCFG2</a></i> 0xFFFFEE08</font></null></ul><a name="MATRIX_MCFG3"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG3 <i> Master Configuration Register 3 (ebi)</i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG3">AT91C_MATRIX_MCFG3</a></i> 0xFFFFEE0C</font></null></ul><a name="MATRIX_MCFG4"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG4 <i> Master Configuration Register 4 (bridge) </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG4">AT91C_MATRIX_MCFG4</a></i> 0xFFFFEE10</font></null></ul><a name="MATRIX_MCFG5"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_MCFG5 <i> Master Configuration Register 5 (mailbox) </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_MCFG5">AT91C_MATRIX_MCFG5</a></i> 0xFFFFEE14</font></null></ul><a name="MATRIX_SCFG0"></a><h4><a href="#MATRIX">MATRIX</a>: <i><a href="AT91SAM9260_h.html#AT91_REG">AT91_REG</a></i> MATRIX_SCFG0 <i> Slave Configuration Register 0 (ram96k) </i></h4><ul><null><font size="-2"><li><b>MATRIX</b> <i><a href="AT91SAM9260_h.html#AT91C_MATRIX_SCFG0">AT91C_MATRIX_SCFG0</a></i> 0xFFFFEE40</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="MATRIX_SLOT_CYCLE"></a><b>MATRIX_SLOT_CYCLE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_SLOT_CYCLE">AT91C_MATRIX_SLOT_CYCLE</a></font></td><td><b>Maximum Number of Allowed Cycles for a Burst</b><br>When the SLOT_CYCLE limit is reached for a burst, it may be broken by another master trying to access this slave.<br>This limit has been placed to avoid locking very slow slave when very long burst are used.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17..16</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE"></a><b>MATRIX_DEFMSTR_TYPE</b><font size="-2"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE">AT91C_MATRIX_DEFMSTR_TYPE</a></font></td><td><b>Default Master Type</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="MATRIX_DEFMSTR_TYPE_NO_DEFMSTR"></a><b>MATRIX_DEFMSTR_TYPE_NO_DEFMSTR</b><font size="-1"><br><a href="AT91SAM9260_h.html#AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR">AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR</a></font></td><td><br>No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.</td></tr>
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