at91sam9261_pmc.html

AT91SAM 系列微控制器的NAND Flash支持代码 描述怎样将NAND Flash和AT91SAM 系列微控制器连接起来。

<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="PMC_PCK0"></a><b>PMC_PCK0</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_PCK0">AT91C_PMC_PCK0</a></font></td><td><b>Programmable Clock Output</b><br>0 = The corresponding programmable clock output is disabled.<br>1 = The corresponding programmable clock output is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="PMC_PCK1"></a><b>PMC_PCK1</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_PCK1">AT91C_PMC_PCK1</a></font></td><td><b>Programmable Clock Output</b><br>0 = The corresponding programmable clock output is disabled.<br>1 = The corresponding programmable clock output is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="PMC_PCK2"></a><b>PMC_PCK2</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_PCK2">AT91C_PMC_PCK2</a></font></td><td><b>Programmable Clock Output</b><br>0 = The corresponding programmable clock output is disabled.<br>1 = The corresponding programmable clock output is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="PMC_PCK3"></a><b>PMC_PCK3</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_PCK3">AT91C_PMC_PCK3</a></font></td><td><b>Programmable Clock Output</b><br>0 = The corresponding programmable clock output is disabled.<br>1 = The corresponding programmable clock output is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="PMC_HCK0"></a><b>PMC_HCK0</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_HCK0">AT91C_PMC_HCK0</a></font></td><td><b>AHB UHP Clock Output</b><br>0 = The corresponding AHB UHP clock output is disabled.<br>1 = The corresponding AHB UHP clock output is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="PMC_HCK1"></a><b>PMC_HCK1</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_HCK1">AT91C_PMC_HCK1</a></font></td><td><b>AHB LCDC Clock Output</b><br>0 = The corresponding AHB LCDC clock output is disabled.<br>1 = The corresponding AHB LCDC clock output is enabled.</td></tr>
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<a name="PMC_SCSR"></a><h4><a href="#PMC">PMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> PMC_SCSR  <i>System Clock Status Register</i></h4><ul><null><font size="-2"><li><b>PMC</b> <i><a href="AT91SAM9261_h.html#AT91C_PMC_SCSR">AT91C_PMC_SCSR</a></i> 0xFFFFFC08</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="PMC_PCK"></a><b>PMC_PCK</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_PCK">AT91C_PMC_PCK</a></font></td><td><b>Processor Clock</b><br>0 = The processor clock is disabled<br>1 = The processor clock is enabled</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">6</td><td align="CENTER"><a name="PMC_UHP"></a><b>PMC_UHP</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_UHP">AT91C_PMC_UHP</a></font></td><td><b>USB Host Port Clock</b><br>0 = The 12/48 MHz clock of the USB Host Port is disabled.<br>1 = The 12/48 MHz clock of the USB Host Port is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">7</td><td align="CENTER"><a name="PMC_UDP"></a><b>PMC_UDP</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_UDP">AT91C_PMC_UDP</a></font></td><td><b>USB Device Port Clock</b><br>0 = The 48 MHz clock of the USB Device Port is disabled<br>1 = The 48 MHz clock of the USB Device Port is enabled</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">8</td><td align="CENTER"><a name="PMC_PCK0"></a><b>PMC_PCK0</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_PCK0">AT91C_PMC_PCK0</a></font></td><td><b>Programmable Clock Output</b><br>0 = The corresponding programmable clock output is disabled.<br>1 = The corresponding programmable clock output is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9</td><td align="CENTER"><a name="PMC_PCK1"></a><b>PMC_PCK1</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_PCK1">AT91C_PMC_PCK1</a></font></td><td><b>Programmable Clock Output</b><br>0 = The corresponding programmable clock output is disabled.<br>1 = The corresponding programmable clock output is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">10</td><td align="CENTER"><a name="PMC_PCK2"></a><b>PMC_PCK2</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_PCK2">AT91C_PMC_PCK2</a></font></td><td><b>Programmable Clock Output</b><br>0 = The corresponding programmable clock output is disabled.<br>1 = The corresponding programmable clock output is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11</td><td align="CENTER"><a name="PMC_PCK3"></a><b>PMC_PCK3</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_PCK3">AT91C_PMC_PCK3</a></font></td><td><b>Programmable Clock Output</b><br>0 = The corresponding programmable clock output is disabled.<br>1 = The corresponding programmable clock output is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="PMC_HCK0"></a><b>PMC_HCK0</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_HCK0">AT91C_PMC_HCK0</a></font></td><td><b>AHB UHP Clock Output</b><br>0 = The corresponding AHB UHP clock output is disabled.<br>1 = The corresponding AHB UHP clock output is enabled.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">17</td><td align="CENTER"><a name="PMC_HCK1"></a><b>PMC_HCK1</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_PMC_HCK1">AT91C_PMC_HCK1</a></font></td><td><b>AHB LCDC Clock Output</b><br>0 = The corresponding AHB LCDC clock output is disabled.<br>1 = The corresponding AHB LCDC clock output is enabled.</td></tr>
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<a name="PMC_PCER"></a><h4><a href="#PMC">PMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> PMC_PCER  <i>Peripheral Clock Enable Register</i></h4><ul><null><font size="-2"><li><b>PMC</b> <i><a href="AT91SAM9261_h.html#AT91C_PMC_PCER">AT91C_PMC_PCER</a></i> 0xFFFFFC10</font></null></ul><br>PID2...PID31: Peripheral Identifier 2 to 31<br>0 = No effect.<br>1 = Enables the peripheral clock.<a name="PMC_PCDR"></a><h4><a href="#PMC">PMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> PMC_PCDR  <i>Peripheral Clock Disable Register</i></h4><ul><null><font size="-2"><li><b>PMC</b> <i><a href="AT91SAM9261_h.html#AT91C_PMC_PCDR">AT91C_PMC_PCDR</a></i> 0xFFFFFC14</font></null></ul><br>PID2...PID31: Peripheral Identifier 2 to 31<br>0 = No effect.<br>1 = Disables the peripheral clock.<a name="PMC_PCSR"></a><h4><a href="#PMC">PMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> PMC_PCSR  <i>Peripheral Clock Status Register</i></h4><ul><null><font size="-2"><li><b>PMC</b> <i><a href="AT91SAM9261_h.html#AT91C_PMC_PCSR">AT91C_PMC_PCSR</a></i> 0xFFFFFC18</font></null></ul><br>PID2...PID31: Peripheral Identifier 2 to 31<br>0 = peripheral clock disabled.<br>1 = peripheral clock enabled.<a name="CKGR_MOR"></a><h4><a href="#PMC">PMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> CKGR_MOR  <i>Main Oscillator Register</i></h4><ul><null><font size="-2"><li><b>PMC</b> <i><a href="AT91SAM9261_h.html#AT91C_PMC_MOR">AT91C_PMC_MOR</a></i> 0xFFFFFC20</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="CKGR_MOSCEN"></a><b>CKGR_MOSCEN</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_MOSCEN">AT91C_CKGR_MOSCEN</a></font></td><td><b>Main Oscillator Enable</b><br>0 = The main oscillator is disabled.<br>1 = The main oscillator is enabled. OSCBYPASS must be set to 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">1</td><td align="CENTER"><a name="CKGR_OSCBYPASS"></a><b>CKGR_OSCBYPASS</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_OSCBYPASS">AT91C_CKGR_OSCBYPASS</a></font></td><td><b>Main Oscillator Bypass</b><br>0 = The main oscillator is not bypassed.<br>1 = The main oscillator is bypassed. MOSCEN bit must be set to 0.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..8</td><td align="CENTER"><a name="CKGR_OSCOUNT"></a><b>CKGR_OSCOUNT</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_OSCOUNT">AT91C_CKGR_OSCOUNT</a></font></td><td><b>Main Oscillator Start-up Time</b><br>Specifies the number of slow clock cycles multiplied by 8 for the main oscillator start-up time.</td></tr>
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<a name="CKGR_MCFR"></a><h4><a href="#PMC">PMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> CKGR_MCFR  <i>Main Clock  Frequency Register</i></h4><ul><null><font size="-2"><li><b>PMC</b> <i><a href="AT91SAM9261_h.html#AT91C_PMC_MCFR">AT91C_PMC_MCFR</a></i> 0xFFFFFC24</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">15..0</td><td align="CENTER"><a name="CKGR_MAINF"></a><b>CKGR_MAINF</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_MAINF">AT91C_CKGR_MAINF</a></font></td><td><b>Main Clock Frequency</b><br>Gives the number of main clock cycles within 16 slow clock periods.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">16</td><td align="CENTER"><a name="CKGR_MAINRDY"></a><b>CKGR_MAINRDY</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_MAINRDY">AT91C_CKGR_MAINRDY</a></font></td><td><b>Main Clock Ready</b><br>0 = FMAIN value is not valid or the main oscillator is disabled.<br>1 = The main oscillator has been enabled previously and MAINF value is available.</td></tr>
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<a name="CKGR_PLLAR"></a><h4><a href="#PMC">PMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> CKGR_PLLAR  <i>PLL A Register</i></h4><ul><null><font size="-2"><li><b>PMC</b> <i><a href="AT91SAM9261_h.html#AT91C_PMC_PLLAR">AT91C_PMC_PLLAR</a></i> 0xFFFFFC28</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="CKGR_DIVA"></a><b>CKGR_DIVA</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_DIVA">AT91C_CKGR_DIVA</a></font></td><td><b>Divider A Selected</b><br>2-255 Divider output is the selected clock divided by DIVA<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_DIVA_0"></a><b>CKGR_DIVA_0</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_DIVA_0">AT91C_CKGR_DIVA_0</a></font></td><td><br>Divider A output is 0</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_DIVA_BYPASS"></a><b>CKGR_DIVA_BYPASS</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_DIVA_BYPASS">AT91C_CKGR_DIVA_BYPASS</a></font></td><td><br>Divider A is bypassed</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">13..8</td><td align="CENTER"><a name="CKGR_PLLACOUNT"></a><b>CKGR_PLLACOUNT</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_PLLACOUNT">AT91C_CKGR_PLLACOUNT</a></font></td><td><b>PLL A Counter</b><br>Specifies the number of slow clock cycles before the LOCKA bit is set in PMC_SR after PMC_PLLA is written.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="CKGR_OUTA"></a><b>CKGR_OUTA</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_OUTA">AT91C_CKGR_OUTA</a></font></td><td><b>PLL A Output Frequency Range</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_OUTA_0"></a><b>CKGR_OUTA_0</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_OUTA_0">AT91C_CKGR_OUTA_0</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_OUTA_1"></a><b>CKGR_OUTA_1</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_OUTA_1">AT91C_CKGR_OUTA_1</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="CKGR_OUTA_2"></a><b>CKGR_OUTA_2</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_OUTA_2">AT91C_CKGR_OUTA_2</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="CKGR_OUTA_3"></a><b>CKGR_OUTA_3</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_OUTA_3">AT91C_CKGR_OUTA_3</a></font></td><td><br>Please refer to the PLLA datasheet</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">26..16</td><td align="CENTER"><a name="CKGR_MULA"></a><b>CKGR_MULA</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_MULA">AT91C_CKGR_MULA</a></font></td><td><b>PLL A Multiplier</b><br>0 = The PLL A is deactivated.<br>1 up to 2047 = The PLL A output frequency is the PLL A input frequency multiplied by MULA + 1.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">29</td><td align="CENTER"><a name="CKGR_SRCA"></a><b>CKGR_SRCA</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_SRCA">AT91C_CKGR_SRCA</a></font></td><td><b></b><br>BE CAREFUL !!! This bit MUST BE SET TO 1.</td></tr>
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<a name="CKGR_PLLBR"></a><h4><a href="#PMC">PMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> CKGR_PLLBR  <i>PLL B Register</i></h4><ul><null><font size="-2"><li><b>PMC</b> <i><a href="AT91SAM9261_h.html#AT91C_PMC_PLLBR">AT91C_PMC_PLLBR</a></i> 0xFFFFFC2C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">7..0</td><td align="CENTER"><a name="CKGR_DIVB"></a><b>CKGR_DIVB</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_DIVB">AT91C_CKGR_DIVB</a></font></td><td><b>Divider B Selected</b><br>2-255 Divider output is the selected clock divided by DIVB<font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_DIVB_0"></a><b>CKGR_DIVB_0</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_DIVB_0">AT91C_CKGR_DIVB_0</a></font></td><td><br>Divider B output is 0</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_DIVB_BYPASS"></a><b>CKGR_DIVB_BYPASS</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_DIVB_BYPASS">AT91C_CKGR_DIVB_BYPASS</a></font></td><td><br>Divider B is bypassed</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">13..8</td><td align="CENTER"><a name="CKGR_PLLBCOUNT"></a><b>CKGR_PLLBCOUNT</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_PLLBCOUNT">AT91C_CKGR_PLLBCOUNT</a></font></td><td><b>PLL B Counter</b><br>Specifies the number of slow clock cycles before the LOCKB bit is set in PMC_SR after PMC_PLLB is written.</td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">15..14</td><td align="CENTER"><a name="CKGR_OUTB"></a><b>CKGR_OUTB</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_OUTB">AT91C_CKGR_OUTB</a></font></td><td><b>PLL B Output Frequency Range</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="CKGR_OUTB_0"></a><b>CKGR_OUTB_0</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_OUTB_0">AT91C_CKGR_OUTB_0</a></font></td><td><br>Please refer to the PLLB datasheet</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="CKGR_OUTB_1"></a><b>CKGR_OUTB_1</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_CKGR_OUTB_1">AT91C_CKGR_OUTB_1</a></font></td><td><br>Please refer to the PLLB datasheet</td></tr>