at91sam9261_sdramc.html

AT91SAM 系列微控制器的NAND Flash支持代码 描述怎样将NAND Flash和AT91SAM 系列微控制器连接起来。

<tr><td align="CENTER">1</td><td align="CENTER"><a name="SDRAMC_TXSR_1"></a><b>SDRAMC_TXSR_1</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_1">AT91C_SDRAMC_TXSR_1</a></font></td><td><br>Value :  1</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SDRAMC_TXSR_2"></a><b>SDRAMC_TXSR_2</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_2">AT91C_SDRAMC_TXSR_2</a></font></td><td><br>Value :  2</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SDRAMC_TXSR_3"></a><b>SDRAMC_TXSR_3</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_3">AT91C_SDRAMC_TXSR_3</a></font></td><td><br>Value :  3</td></tr>
<tr><td align="CENTER">4</td><td align="CENTER"><a name="SDRAMC_TXSR_4"></a><b>SDRAMC_TXSR_4</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_4">AT91C_SDRAMC_TXSR_4</a></font></td><td><br>Value :  4</td></tr>
<tr><td align="CENTER">5</td><td align="CENTER"><a name="SDRAMC_TXSR_5"></a><b>SDRAMC_TXSR_5</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_5">AT91C_SDRAMC_TXSR_5</a></font></td><td><br>Value :  5</td></tr>
<tr><td align="CENTER">6</td><td align="CENTER"><a name="SDRAMC_TXSR_6"></a><b>SDRAMC_TXSR_6</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_6">AT91C_SDRAMC_TXSR_6</a></font></td><td><br>Value :  6</td></tr>
<tr><td align="CENTER">7</td><td align="CENTER"><a name="SDRAMC_TXSR_7"></a><b>SDRAMC_TXSR_7</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_7">AT91C_SDRAMC_TXSR_7</a></font></td><td><br>Value :  7</td></tr>
<tr><td align="CENTER">8</td><td align="CENTER"><a name="SDRAMC_TXSR_8"></a><b>SDRAMC_TXSR_8</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_8">AT91C_SDRAMC_TXSR_8</a></font></td><td><br>Value :  8</td></tr>
<tr><td align="CENTER">9</td><td align="CENTER"><a name="SDRAMC_TXSR_9"></a><b>SDRAMC_TXSR_9</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_9">AT91C_SDRAMC_TXSR_9</a></font></td><td><br>Value :  9</td></tr>
<tr><td align="CENTER">10</td><td align="CENTER"><a name="SDRAMC_TXSR_10"></a><b>SDRAMC_TXSR_10</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_10">AT91C_SDRAMC_TXSR_10</a></font></td><td><br>Value : 10</td></tr>
<tr><td align="CENTER">11</td><td align="CENTER"><a name="SDRAMC_TXSR_11"></a><b>SDRAMC_TXSR_11</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_11">AT91C_SDRAMC_TXSR_11</a></font></td><td><br>Value : 11</td></tr>
<tr><td align="CENTER">12</td><td align="CENTER"><a name="SDRAMC_TXSR_12"></a><b>SDRAMC_TXSR_12</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_12">AT91C_SDRAMC_TXSR_12</a></font></td><td><br>Value : 12</td></tr>
<tr><td align="CENTER">13</td><td align="CENTER"><a name="SDRAMC_TXSR_13"></a><b>SDRAMC_TXSR_13</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_13">AT91C_SDRAMC_TXSR_13</a></font></td><td><br>Value : 13</td></tr>
<tr><td align="CENTER">14</td><td align="CENTER"><a name="SDRAMC_TXSR_14"></a><b>SDRAMC_TXSR_14</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_14">AT91C_SDRAMC_TXSR_14</a></font></td><td><br>Value : 14</td></tr>
<tr><td align="CENTER">15</td><td align="CENTER"><a name="SDRAMC_TXSR_15"></a><b>SDRAMC_TXSR_15</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TXSR_15">AT91C_SDRAMC_TXSR_15</a></font></td><td><br>Value : 15</td></tr>
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<a name="SDRAMC_HSR"></a><h4><a href="#SDRAMC">SDRAMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> SDRAMC_HSR  <i>SDRAM Controller High Speed Register</i></h4><ul><null><font size="-2"><li><b>SDRAMC</b> <i><a href="AT91SAM9261_h.html#AT91C_SDRAMC_HSR">AT91C_SDRAMC_HSR</a></i> 0xFFFFEA0C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SDRAMC_DA"></a><b>SDRAMC_DA</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_DA">AT91C_SDRAMC_DA</a></font></td><td><b>Decode Cycle Enable Bit</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SDRAMC_DA_DISABLE"></a><b>SDRAMC_DA_DISABLE</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_DA_DISABLE">AT91C_SDRAMC_DA_DISABLE</a></font></td><td><br>Disable Decode Cycle</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SDRAMC_DA_ENABLE"></a><b>SDRAMC_DA_ENABLE</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_DA_ENABLE">AT91C_SDRAMC_DA_ENABLE</a></font></td><td><br>Enable Decode Cycle</td></tr>
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<a name="SDRAMC_LPR"></a><h4><a href="#SDRAMC">SDRAMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> SDRAMC_LPR  <i>SDRAM Controller Low Power Register</i></h4><ul><null><font size="-2"><li><b>SDRAMC</b> <i><a href="AT91SAM9261_h.html#AT91C_SDRAMC_LPR">AT91C_SDRAMC_LPR</a></i> 0xFFFFEA10</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">1..0</td><td align="CENTER"><a name="SDRAMC_LPCB"></a><b>SDRAMC_LPCB</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_LPCB">AT91C_SDRAMC_LPCB</a></font></td><td><b>Low-power Configurations</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SDRAMC_LPCB_DISABLE"></a><b>SDRAMC_LPCB_DISABLE</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_LPCB_DISABLE">AT91C_SDRAMC_LPCB_DISABLE</a></font></td><td><br>Disable Low Power Features</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SDRAMC_LPCB_SELF_REFRESH"></a><b>SDRAMC_LPCB_SELF_REFRESH</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_LPCB_SELF_REFRESH">AT91C_SDRAMC_LPCB_SELF_REFRESH</a></font></td><td><br>Enable SELF_REFRESH</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SDRAMC_LPCB_POWER_DOWN"></a><b>SDRAMC_LPCB_POWER_DOWN</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_LPCB_POWER_DOWN">AT91C_SDRAMC_LPCB_POWER_DOWN</a></font></td><td><br>Enable POWER_DOWN</td></tr>
<tr><td align="CENTER">3</td><td align="CENTER"><a name="SDRAMC_LPCB_DEEP_POWER_DOWN"></a><b>SDRAMC_LPCB_DEEP_POWER_DOWN</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN">AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN</a></font></td><td><br>Enable DEEP_POWER_DOWN</td></tr>
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<tr><td align="CENTER" bgcolor="#FFFFCC">6..4</td><td align="CENTER"><a name="SDRAMC_PASR"></a><b>SDRAMC_PASR</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_PASR">AT91C_SDRAMC_PASR</a></font></td><td><b>Partial Array Self Refresh (only for Low Power SDRAM)</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">9..8</td><td align="CENTER"><a name="SDRAMC_TCSR"></a><b>SDRAMC_TCSR</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TCSR">AT91C_SDRAMC_TCSR</a></font></td><td><b>Temperature Compensated Self Refresh (only for Low Power SDRAM)</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">11..10</td><td align="CENTER"><a name="SDRAMC_DS"></a><b>SDRAMC_DS</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_DS">AT91C_SDRAMC_DS</a></font></td><td><b>Drive Strenght (only for Low Power SDRAM)</b></td></tr>
<tr><td align="CENTER" bgcolor="#FFFFCC">13..12</td><td align="CENTER"><a name="SDRAMC_TIMEOUT"></a><b>SDRAMC_TIMEOUT</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TIMEOUT">AT91C_SDRAMC_TIMEOUT</a></font></td><td><b>Time to define when Low Power Mode is enabled</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SDRAMC_TIMEOUT_0_CLK_CYCLES"></a><b>SDRAMC_TIMEOUT_0_CLK_CYCLES</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES">AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES</a></font></td><td><br>Activate SDRAM Low Power Mode Immediately</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SDRAMC_TIMEOUT_64_CLK_CYCLES"></a><b>SDRAMC_TIMEOUT_64_CLK_CYCLES</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES">AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES</a></font></td><td><br>Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer</td></tr>
<tr><td align="CENTER">2</td><td align="CENTER"><a name="SDRAMC_TIMEOUT_128_CLK_CYCLES"></a><b>SDRAMC_TIMEOUT_128_CLK_CYCLES</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES">AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES</a></font></td><td><br>Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer</td></tr>
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<a name="SDRAMC_IER"></a><h4><a href="#SDRAMC">SDRAMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> SDRAMC_IER  <i>SDRAM Controller Interrupt Enable Register</i></h4><ul><null><font size="-2"><li><b>SDRAMC</b> <i><a href="AT91SAM9261_h.html#AT91C_SDRAMC_IER">AT91C_SDRAMC_IER</a></i> 0xFFFFEA14</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SDRAMC_RES"></a><b>SDRAMC_RES</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_RES">AT91C_SDRAMC_RES</a></font></td><td><b>Refresh Error Status</b></td></tr>
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<a name="SDRAMC_IDR"></a><h4><a href="#SDRAMC">SDRAMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> SDRAMC_IDR  <i>SDRAM Controller Interrupt Disable Register</i></h4><ul><null><font size="-2"><li><b>SDRAMC</b> <i><a href="AT91SAM9261_h.html#AT91C_SDRAMC_IDR">AT91C_SDRAMC_IDR</a></i> 0xFFFFEA18</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SDRAMC_RES"></a><b>SDRAMC_RES</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_RES">AT91C_SDRAMC_RES</a></font></td><td><b>Refresh Error Status</b></td></tr>
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<a name="SDRAMC_IMR"></a><h4><a href="#SDRAMC">SDRAMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> SDRAMC_IMR  <i>SDRAM Controller Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>SDRAMC</b> <i><a href="AT91SAM9261_h.html#AT91C_SDRAMC_IMR">AT91C_SDRAMC_IMR</a></i> 0xFFFFEA1C</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SDRAMC_RES"></a><b>SDRAMC_RES</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_RES">AT91C_SDRAMC_RES</a></font></td><td><b>Refresh Error Status</b></td></tr>
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<a name="SDRAMC_ISR"></a><h4><a href="#SDRAMC">SDRAMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> SDRAMC_ISR  <i>SDRAM Controller Interrupt Mask Register</i></h4><ul><null><font size="-2"><li><b>SDRAMC</b> <i><a href="AT91SAM9261_h.html#AT91C_SDRAMC_ISR">AT91C_SDRAMC_ISR</a></i> 0xFFFFEA20</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">0</td><td align="CENTER"><a name="SDRAMC_RES"></a><b>SDRAMC_RES</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_RES">AT91C_SDRAMC_RES</a></font></td><td><b>Refresh Error Status</b></td></tr>
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<a name="SDRAMC_MDR"></a><h4><a href="#SDRAMC">SDRAMC</a>: <i><a href="AT91SAM9261_h.html#AT91_REG">AT91_REG</a></i> SDRAMC_MDR  <i>SDRAM Memory Device Register</i></h4><ul><null><font size="-2"><li><b>SDRAMC</b> <i><a href="AT91SAM9261_h.html#AT91C_SDRAMC_MDR">AT91C_SDRAMC_MDR</a></i> 0xFFFFEA24</font></null></ul><table border=1 cellpadding=0 cellspacing=0 width="100%"><null><th bgcolor="#FFFFCC"><b>Offset</b></th><th bgcolor="#FFFFCC"><b>Name</b></th><th bgcolor="#FFFFCC"><b>Description</b></th><tr><td align="CENTER" bgcolor="#FFFFCC">1..0</td><td align="CENTER"><a name="SDRAMC_MD"></a><b>SDRAMC_MD</b><font size="-2"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_MD">AT91C_SDRAMC_MD</a></font></td><td><b>Memory Device Type</b><font size="-1"><table bgcolor="#E3F2FF" border=1 cellpadding=0 cellspacing=0 width="100%"><null><th><b>Value</b></th><th><b>Label</b></th><th><b>Description</b></th><tr><td align="CENTER">0</td><td align="CENTER"><a name="SDRAMC_MD_SDRAM"></a><b>SDRAMC_MD_SDRAM</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_MD_SDRAM">AT91C_SDRAMC_MD_SDRAM</a></font></td><td><br>SDRAM Mode</td></tr>
<tr><td align="CENTER">1</td><td align="CENTER"><a name="SDRAMC_MD_LOW_POWER_SDRAM"></a><b>SDRAMC_MD_LOW_POWER_SDRAM</b><font size="-1"><br><a href="AT91SAM9261_h.html#AT91C_SDRAMC_MD_LOW_POWER_SDRAM">AT91C_SDRAMC_MD_LOW_POWER_SDRAM</a></font></td><td><br>SDRAM Low Power Mode</td></tr>
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