at91sam9261.rdf

AT91SAM 系列微控制器的NAND Flash支持代码 描述怎样将NAND Flash和AT91SAM 系列微控制器连接起来。

AT91C_SMC_SETUP1.description=" Setup Register for CS 1"
AT91C_SMC_SETUP1.helpkey=" Setup Register for CS 1"
AT91C_SMC_SETUP1.access=memorymapped
AT91C_SMC_SETUP1.address=0xFFFFEC10
AT91C_SMC_SETUP1.width=32
AT91C_SMC_SETUP1.byteEndian=little
AT91C_SMC_CTRL5.name="AT91C_SMC_CTRL5"
AT91C_SMC_CTRL5.description=" Control Register for CS 5"
AT91C_SMC_CTRL5.helpkey=" Control Register for CS 5"
AT91C_SMC_CTRL5.access=memorymapped
AT91C_SMC_CTRL5.address=0xFFFFEC5C
AT91C_SMC_CTRL5.width=32
AT91C_SMC_CTRL5.byteEndian=little
AT91C_SMC_PULSE6.name="AT91C_SMC_PULSE6"
AT91C_SMC_PULSE6.description=" Pulse Register for CS 6"
AT91C_SMC_PULSE6.helpkey=" Pulse Register for CS 6"
AT91C_SMC_PULSE6.access=memorymapped
AT91C_SMC_PULSE6.address=0xFFFFEC64
AT91C_SMC_PULSE6.width=32
AT91C_SMC_PULSE6.byteEndian=little
AT91C_SMC_CTRL6.name="AT91C_SMC_CTRL6"
AT91C_SMC_CTRL6.description=" Control Register for CS 6"
AT91C_SMC_CTRL6.helpkey=" Control Register for CS 6"
AT91C_SMC_CTRL6.access=memorymapped
AT91C_SMC_CTRL6.address=0xFFFFEC6C
AT91C_SMC_CTRL6.width=32
AT91C_SMC_CTRL6.byteEndian=little
AT91C_SMC_PULSE7.name="AT91C_SMC_PULSE7"
AT91C_SMC_PULSE7.description=" Pulse Register for CS 7"
AT91C_SMC_PULSE7.helpkey=" Pulse Register for CS 7"
AT91C_SMC_PULSE7.access=memorymapped
AT91C_SMC_PULSE7.address=0xFFFFEC74
AT91C_SMC_PULSE7.width=32
AT91C_SMC_PULSE7.byteEndian=little
AT91C_SMC_CTRL0.name="AT91C_SMC_CTRL0"
AT91C_SMC_CTRL0.description=" Control Register for CS 0"
AT91C_SMC_CTRL0.helpkey=" Control Register for CS 0"
AT91C_SMC_CTRL0.access=memorymapped
AT91C_SMC_CTRL0.address=0xFFFFEC0C
AT91C_SMC_CTRL0.width=32
AT91C_SMC_CTRL0.byteEndian=little
AT91C_SMC_PULSE1.name="AT91C_SMC_PULSE1"
AT91C_SMC_PULSE1.description=" Pulse Register for CS 1"
AT91C_SMC_PULSE1.helpkey=" Pulse Register for CS 1"
AT91C_SMC_PULSE1.access=memorymapped
AT91C_SMC_PULSE1.address=0xFFFFEC14
AT91C_SMC_PULSE1.width=32
AT91C_SMC_PULSE1.byteEndian=little
AT91C_SMC_SETUP7.name="AT91C_SMC_SETUP7"
AT91C_SMC_SETUP7.description=" Setup Register for CS 7"
AT91C_SMC_SETUP7.helpkey=" Setup Register for CS 7"
AT91C_SMC_SETUP7.access=memorymapped
AT91C_SMC_SETUP7.address=0xFFFFEC70
AT91C_SMC_SETUP7.width=32
AT91C_SMC_SETUP7.byteEndian=little
AT91C_SMC_CYCLE7.name="AT91C_SMC_CYCLE7"
AT91C_SMC_CYCLE7.description=" Cycle Register for CS 7"
AT91C_SMC_CYCLE7.helpkey=" Cycle Register for CS 7"
AT91C_SMC_CYCLE7.access=memorymapped
AT91C_SMC_CYCLE7.address=0xFFFFEC78
AT91C_SMC_CYCLE7.width=32
AT91C_SMC_CYCLE7.byteEndian=little
# ========== Register definition for MATRIX peripheral ========== 
AT91C_MATRIX_SCFG0.name="AT91C_MATRIX_SCFG0"
AT91C_MATRIX_SCFG0.description=" Slave Configuration Register 0"
AT91C_MATRIX_SCFG0.helpkey=" Slave Configuration Register 0"
AT91C_MATRIX_SCFG0.access=memorymapped
AT91C_MATRIX_SCFG0.address=0xFFFFEE04
AT91C_MATRIX_SCFG0.width=32
AT91C_MATRIX_SCFG0.byteEndian=little
AT91C_MATRIX_EBICSA.name="AT91C_MATRIX_EBICSA"
AT91C_MATRIX_EBICSA.description=" Slave 3 Special Function Register"
AT91C_MATRIX_EBICSA.helpkey=" Slave 3 Special Function Register"
AT91C_MATRIX_EBICSA.access=memorymapped
AT91C_MATRIX_EBICSA.address=0xFFFFEE30
AT91C_MATRIX_EBICSA.width=32
AT91C_MATRIX_EBICSA.byteEndian=little
AT91C_MATRIX_SCFG3.name="AT91C_MATRIX_SCFG3"
AT91C_MATRIX_SCFG3.description=" Slave Configuration Register 3"
AT91C_MATRIX_SCFG3.helpkey=" Slave Configuration Register 3"
AT91C_MATRIX_SCFG3.access=memorymapped
AT91C_MATRIX_SCFG3.address=0xFFFFEE10
AT91C_MATRIX_SCFG3.width=32
AT91C_MATRIX_SCFG3.byteEndian=little
AT91C_MATRIX_SCFG1.name="AT91C_MATRIX_SCFG1"
AT91C_MATRIX_SCFG1.description=" Slave Configuration Register 1"
AT91C_MATRIX_SCFG1.helpkey=" Slave Configuration Register 1"
AT91C_MATRIX_SCFG1.access=memorymapped
AT91C_MATRIX_SCFG1.address=0xFFFFEE08
AT91C_MATRIX_SCFG1.width=32
AT91C_MATRIX_SCFG1.byteEndian=little
AT91C_MATRIX_MCFG.name="AT91C_MATRIX_MCFG"
AT91C_MATRIX_MCFG.description=" Master Configuration Register"
AT91C_MATRIX_MCFG.helpkey=" Master Configuration Register"
AT91C_MATRIX_MCFG.access=memorymapped
AT91C_MATRIX_MCFG.address=0xFFFFEE00
AT91C_MATRIX_MCFG.width=32
AT91C_MATRIX_MCFG.byteEndian=little
AT91C_MATRIX_MCFG.type=enum
AT91C_MATRIX_MCFG.enum.0.name=*** Write only ***
AT91C_MATRIX_MCFG.enum.1.name=Error
AT91C_MATRIX_VERSION.name="AT91C_MATRIX_VERSION"
AT91C_MATRIX_VERSION.description=" Version Register"
AT91C_MATRIX_VERSION.helpkey=" Version Register"
AT91C_MATRIX_VERSION.access=memorymapped
AT91C_MATRIX_VERSION.address=0xFFFFEE44
AT91C_MATRIX_VERSION.width=32
AT91C_MATRIX_VERSION.byteEndian=little
AT91C_MATRIX_VERSION.permission.write=none
AT91C_MATRIX_USBPCR.name="AT91C_MATRIX_USBPCR"
AT91C_MATRIX_USBPCR.description=" Slave 4 Special Function Register"
AT91C_MATRIX_USBPCR.helpkey=" Slave 4 Special Function Register"
AT91C_MATRIX_USBPCR.access=memorymapped
AT91C_MATRIX_USBPCR.address=0xFFFFEE34
AT91C_MATRIX_USBPCR.width=32
AT91C_MATRIX_USBPCR.byteEndian=little
AT91C_MATRIX_TCMR.name="AT91C_MATRIX_TCMR"
AT91C_MATRIX_TCMR.description=" Slave 0 Special Function Register"
AT91C_MATRIX_TCMR.helpkey=" Slave 0 Special Function Register"
AT91C_MATRIX_TCMR.access=memorymapped
AT91C_MATRIX_TCMR.address=0xFFFFEE24
AT91C_MATRIX_TCMR.width=32
AT91C_MATRIX_TCMR.byteEndian=little
AT91C_MATRIX_SCFG4.name="AT91C_MATRIX_SCFG4"
AT91C_MATRIX_SCFG4.description=" Slave Configuration Register 4"
AT91C_MATRIX_SCFG4.helpkey=" Slave Configuration Register 4"
AT91C_MATRIX_SCFG4.access=memorymapped
AT91C_MATRIX_SCFG4.address=0xFFFFEE14
AT91C_MATRIX_SCFG4.width=32
AT91C_MATRIX_SCFG4.byteEndian=little
AT91C_MATRIX_SCFG2.name="AT91C_MATRIX_SCFG2"
AT91C_MATRIX_SCFG2.description=" Slave Configuration Register 2"
AT91C_MATRIX_SCFG2.helpkey=" Slave Configuration Register 2"
AT91C_MATRIX_SCFG2.access=memorymapped
AT91C_MATRIX_SCFG2.address=0xFFFFEE0C
AT91C_MATRIX_SCFG2.width=32
AT91C_MATRIX_SCFG2.byteEndian=little
# ========== Register definition for AIC peripheral ========== 
AT91C_AIC_ICCR.name="AT91C_AIC_ICCR"
AT91C_AIC_ICCR.description="Interrupt Clear Command Register"
AT91C_AIC_ICCR.helpkey="Interrupt Clear Command Register"
AT91C_AIC_ICCR.access=memorymapped
AT91C_AIC_ICCR.address=0xFFFFF128
AT91C_AIC_ICCR.width=32
AT91C_AIC_ICCR.byteEndian=little
AT91C_AIC_ICCR.type=enum
AT91C_AIC_ICCR.enum.0.name=*** Write only ***
AT91C_AIC_ICCR.enum.1.name=Error
AT91C_AIC_IECR.name="AT91C_AIC_IECR"
AT91C_AIC_IECR.description="Interrupt Enable Command Register"
AT91C_AIC_IECR.helpkey="Interrupt Enable Command Register"
AT91C_AIC_IECR.access=memorymapped
AT91C_AIC_IECR.address=0xFFFFF120
AT91C_AIC_IECR.width=32
AT91C_AIC_IECR.byteEndian=little
AT91C_AIC_IECR.type=enum
AT91C_AIC_IECR.enum.0.name=*** Write only ***
AT91C_AIC_IECR.enum.1.name=Error
AT91C_AIC_SMR.name="AT91C_AIC_SMR"
AT91C_AIC_SMR.description="Source Mode Register"
AT91C_AIC_SMR.helpkey="Source Mode Register"
AT91C_AIC_SMR.access=memorymapped
AT91C_AIC_SMR.address=0xFFFFF000
AT91C_AIC_SMR.width=32
AT91C_AIC_SMR.byteEndian=little
AT91C_AIC_ISCR.name="AT91C_AIC_ISCR"
AT91C_AIC_ISCR.description="Interrupt Set Command Register"
AT91C_AIC_ISCR.helpkey="Interrupt Set Command Register"
AT91C_AIC_ISCR.access=memorymapped
AT91C_AIC_ISCR.address=0xFFFFF12C
AT91C_AIC_ISCR.width=32
AT91C_AIC_ISCR.byteEndian=little
AT91C_AIC_ISCR.type=enum
AT91C_AIC_ISCR.enum.0.name=*** Write only ***
AT91C_AIC_ISCR.enum.1.name=Error
AT91C_AIC_EOICR.name="AT91C_AIC_EOICR"
AT91C_AIC_EOICR.description="End of Interrupt Command Register"
AT91C_AIC_EOICR.helpkey="End of Interrupt Command Register"
AT91C_AIC_EOICR.access=memorymapped
AT91C_AIC_EOICR.address=0xFFFFF130
AT91C_AIC_EOICR.width=32
AT91C_AIC_EOICR.byteEndian=little
AT91C_AIC_EOICR.type=enum
AT91C_AIC_EOICR.enum.0.name=*** Write only ***
AT91C_AIC_EOICR.enum.1.name=Error
AT91C_AIC_DCR.name="AT91C_AIC_DCR"
AT91C_AIC_DCR.description="Debug Control Register (Protect)"
AT91C_AIC_DCR.helpkey="Debug Control Register (Protect)"
AT91C_AIC_DCR.access=memorymapped
AT91C_AIC_DCR.address=0xFFFFF138
AT91C_AIC_DCR.width=32
AT91C_AIC_DCR.byteEndian=little
AT91C_AIC_FFER.name="AT91C_AIC_FFER"
AT91C_AIC_FFER.description="Fast Forcing Enable Register"
AT91C_AIC_FFER.helpkey="Fast Forcing Enable Register"
AT91C_AIC_FFER.access=memorymapped
AT91C_AIC_FFER.address=0xFFFFF140
AT91C_AIC_FFER.width=32
AT91C_AIC_FFER.byteEndian=little
AT91C_AIC_FFER.type=enum
AT91C_AIC_FFER.enum.0.name=*** Write only ***
AT91C_AIC_FFER.enum.1.name=Error
AT91C_AIC_SVR.name="AT91C_AIC_SVR"
AT91C_AIC_SVR.description="Source Vector Register"
AT91C_AIC_SVR.helpkey="Source Vector Register"
AT91C_AIC_SVR.access=memorymapped
AT91C_AIC_SVR.address=0xFFFFF080
AT91C_AIC_SVR.width=32
AT91C_AIC_SVR.byteEndian=little
AT91C_AIC_SPU.name="AT91C_AIC_SPU"
AT91C_AIC_SPU.description="Spurious Vector Register"
AT91C_AIC_SPU.helpkey="Spurious Vector Register"
AT91C_AIC_SPU.access=memorymapped
AT91C_AIC_SPU.address=0xFFFFF134
AT91C_AIC_SPU.width=32
AT91C_AIC_SPU.byteEndian=little
AT91C_AIC_FFDR.name="AT91C_AIC_FFDR"
AT91C_AIC_FFDR.description="Fast Forcing Disable Register"
AT91C_AIC_FFDR.helpkey="Fast Forcing Disable Register"
AT91C_AIC_FFDR.access=memorymapped
AT91C_AIC_FFDR.address=0xFFFFF144
AT91C_AIC_FFDR.width=32
AT91C_AIC_FFDR.byteEndian=little
AT91C_AIC_FFDR.type=enum
AT91C_AIC_FFDR.enum.0.name=*** Write only ***
AT91C_AIC_FFDR.enum.1.name=Error
AT91C_AIC_FVR.name="AT91C_AIC_FVR"
AT91C_AIC_FVR.description="FIQ Vector Register"
AT91C_AIC_FVR.helpkey="FIQ Vector Register"
AT91C_AIC_FVR.access=memorymapped
AT91C_AIC_FVR.address=0xFFFFF104
AT91C_AIC_FVR.width=32
AT91C_AIC_FVR.byteEndian=little
AT91C_AIC_FVR.permission.write=none
AT91C_AIC_FFSR.name="AT91C_AIC_FFSR"
AT91C_AIC_FFSR.description="Fast Forcing Status Register"
AT91C_AIC_FFSR.helpkey="Fast Forcing Status Register"
AT91C_AIC_FFSR.access=memorymapped
AT91C_AIC_FFSR.address=0xFFFFF148
AT91C_AIC_FFSR.width=32
AT91C_AIC_FFSR.byteEndian=little
AT91C_AIC_FFSR.permission.write=none
AT91C_AIC_IMR.name="AT91C_AIC_IMR"
AT91C_AIC_IMR.description="Interrupt Mask Register"
AT91C_AIC_IMR.helpkey="Interrupt Mask Register"
AT91C_AIC_IMR.access=memorymapped
AT91C_AIC_IMR.address=0xFFFFF110
AT91C_AIC_IMR.width=32
AT91C_AIC_IMR.byteEndian=little
AT91C_AIC_IMR.permission.write=none
AT91C_AIC_ISR.name="AT91C_AIC_ISR"
AT91C_AIC_ISR.description="Interrupt Status Register"
AT91C_AIC_ISR.helpkey="Interrupt Status Register"
AT91C_AIC_ISR.access=memorymapped
AT91C_AIC_ISR.address=0xFFFFF108
AT91C_AIC_ISR.width=32
AT91C_AIC_ISR.byteEndian=little
AT91C_AIC_ISR.permission.write=none
AT91C_AIC_IVR.name="AT91C_AIC_IVR"
AT91C_AIC_IVR.description="IRQ Vector Register"
AT91C_AIC_IVR.helpkey="IRQ Vector Register"
AT91C_AIC_IVR.access=memorymapped
AT91C_AIC_IVR.address=0xFFFFF100
AT91C_AIC_IVR.width=32
AT91C_AIC_IVR.byteEndian=little
AT91C_AIC_IVR.permission.write=none
AT91C_AIC_IDCR.name="AT91C_AIC_IDCR"
AT91C_AIC_IDCR.description="Interrupt Disable Command Register"
AT91C_AIC_IDCR.helpkey="Interrupt Disable Command Register"
AT91C_AIC_IDCR.access=memorymapped
AT91C_AIC_IDCR.address=0xFFFFF124
AT91C_AIC_IDCR.width=32
AT91C_AIC_IDCR.byteEndian=little
AT91C_AIC_IDCR.type=enum
AT91C_AIC_IDCR.enum.0.name=*** Write only ***
AT91C_AIC_IDCR.enum.1.name=Error
AT91C_AIC_CISR.name="AT91C_AIC_CISR"
AT91C_AIC_CISR.description="Core Interrupt Status Register"
AT91C_AIC_CISR.helpkey="Core Interrupt Status Register"
AT91C_AIC_CISR.access=memorymapped
AT91C_AIC_CISR.address=0xFFFFF114
AT91C_AIC_CISR.width=32
AT91C_AIC_CISR.byteEndian=little
AT91C_AIC_CISR.permission.write=none
AT91C_AIC_IPR.name="AT91C_AIC_IPR"
AT91C_AIC_IPR.description="Interrupt Pending Register"
AT91C_AIC_IPR.helpkey="Interrupt Pending Register"
AT91C_AIC_IPR.access=memorymapped
AT91C_AIC_IPR.address=0xFFFFF10C
AT91C_AIC_IPR.width=32
AT91C_AIC_IPR.byteEndian=little
AT91C_AIC_IPR.permission.write=none
# ========== Register definition for PDC_DBGU peripheral ========== 
AT91C_DBGU_TNCR.name="AT91C_DBGU_TNCR"
AT91C_DBGU_TNCR.description="Transmit Next Counter Register"
AT91C_DBGU_TNCR.helpkey="Transmit Next Counter Register"
AT91C_DBGU_TNCR.access=memorymapped
AT91C_DBGU_TNCR.address=0xFFFFF31C
AT91C_DBGU_TNCR.width=32
AT91C_DBGU_TNCR.byteEndian=little
AT91C_DBGU_RNCR.name="AT91C_DBGU_RNCR"
AT91C_DBGU_RNCR.description="Receive Next Counter Register"
AT91C_DBGU_RNCR.helpkey="Receive Next Counter Register"
AT91C_DBGU_RNCR.access=memorymapped
AT91C_DBGU_RNCR.address=0xFFFFF314
AT91C_DBGU_RNCR.width=32
AT91C_DBGU_RNCR.byteEndian=little
AT91C_DBGU_PTCR.name="AT91C_DBGU_PTCR"
AT91C_DBGU_PTCR.description="PDC Transfer Control Register"
AT91C_DBGU_PTCR.helpkey="PDC Transfer Control Register"
AT91C_DBGU_PTCR.access=memorymapped
AT91C_DBGU_PTCR.address=0xFFFFF320
AT91C_DBGU_PTCR.width=32
AT91C_DBGU_PTCR.byteEndian=little
AT91C_DBGU_PTCR.type=enum
AT91C_DBGU_PTCR.enum.0.name=*** Write only ***
AT91C_DBGU_PTCR.enum.1.name=Error
AT91C_DBGU_PTSR.name="AT91C_DBGU_PTSR"
AT91C_DBGU_PTSR.description="PDC Transfer Status Register"
AT91C_DBGU_PTSR.helpkey="PDC Transfer Status Register"