📄 at91sam9261.rdf
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# ----------------------------------------------------------------------------
# ATMEL Microcontroller Software Support - ROUSSET -
# ----------------------------------------------------------------------------
# DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
# IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
# MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
# DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
# OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
# LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
# NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
# EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
# ----------------------------------------------------------------------------
# File Name : AT91SAM9261.h
# Object : AT91SAM9261 definitions
# Generated : AT91 SW Application Group 09/12/2005 (15:39:28)
#
# CVS Reference : /AT91SAM9261.pl/1.12/Mon Sep 12 13:26:48 2005//
# CVS Reference : /SYS_SAM9261.pl/1.5/Thu Nov 18 13:22:33 2004//
# CVS Reference : /HMATRIX1_SAM9261.pl/1.2/Mon Nov 8 16:38:17 2004//
# CVS Reference : /PMC_SAM9261.pl/1.4/Fri Sep 9 15:24:01 2005//
# CVS Reference : /HSMC3_SAM9261.pl/1.1/Tue Nov 16 09:16:07 2004//
# CVS Reference : /SHDWC_SAM9261.pl/1.1/Tue Mar 8 14:46:52 2005//
# CVS Reference : /UDP_SAM9261.pl/1.1/Tue May 10 12:39:24 2005//
# CVS Reference : /HSDRAMC1_6100A.pl/1.2/Mon Aug 9 10:52:25 2004//
# CVS Reference : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
# CVS Reference : /PDC_6074C.pl/1.2/Thu Feb 3 09:02:11 2005//
# CVS Reference : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
# CVS Reference : /PIO_6057A.pl/1.2/Thu Feb 3 10:29:42 2005//
# CVS Reference : /RSTC_6098A.pl/1.3/Thu Nov 4 13:57:00 2004//
# CVS Reference : /RTTC_6081A.pl/1.2/Thu Nov 4 13:57:22 2004//
# CVS Reference : /PITC_6079A.pl/1.2/Thu Nov 4 13:56:22 2004//
# CVS Reference : /WDTC_6080A.pl/1.3/Thu Nov 4 13:58:52 2004//
# CVS Reference : /TC_6082A.pl/1.7/Wed Mar 9 16:31:51 2005//
# CVS Reference : /MCI_6101A.pl/1.1/Tue Jul 13 06:33:59 2004//
# CVS Reference : /TWI_6061A.pl/1.1/Tue Jul 13 06:38:23 2004//
# CVS Reference : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
# CVS Reference : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005//
# CVS Reference : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
# CVS Reference : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
# CVS Reference : /LCDC_6063A.pl/1.2/Wed Nov 24 15:55:51 2004//
# ----------------------------------------------------------------------------
rdf.version=1
~sysinclude=arm_default.rdf
~sysinclude=arm_status.rdf
# ========== Register definition for SYS peripheral ==========
AT91C_SYS_GPBR3.name="AT91C_SYS_GPBR3"
AT91C_SYS_GPBR3.description="General Purpose Register 3"
AT91C_SYS_GPBR3.helpkey="General Purpose Register 3"
AT91C_SYS_GPBR3.access=memorymapped
AT91C_SYS_GPBR3.address=0xFFFFFD5C
AT91C_SYS_GPBR3.width=32
AT91C_SYS_GPBR3.byteEndian=little
AT91C_SYS_GPBR1.name="AT91C_SYS_GPBR1"
AT91C_SYS_GPBR1.description="General Purpose Register 1"
AT91C_SYS_GPBR1.helpkey="General Purpose Register 1"
AT91C_SYS_GPBR1.access=memorymapped
AT91C_SYS_GPBR1.address=0xFFFFFD54
AT91C_SYS_GPBR1.width=32
AT91C_SYS_GPBR1.byteEndian=little
AT91C_SYS_GPBR2.name="AT91C_SYS_GPBR2"
AT91C_SYS_GPBR2.description="General Purpose Register 2"
AT91C_SYS_GPBR2.helpkey="General Purpose Register 2"
AT91C_SYS_GPBR2.access=memorymapped
AT91C_SYS_GPBR2.address=0xFFFFFD58
AT91C_SYS_GPBR2.width=32
AT91C_SYS_GPBR2.byteEndian=little
AT91C_SYS_GPBR0.name="AT91C_SYS_GPBR0"
AT91C_SYS_GPBR0.description="General Purpose Register 0"
AT91C_SYS_GPBR0.helpkey="General Purpose Register 0"
AT91C_SYS_GPBR0.access=memorymapped
AT91C_SYS_GPBR0.address=0xFFFFFD50
AT91C_SYS_GPBR0.width=32
AT91C_SYS_GPBR0.byteEndian=little
# ========== Register definition for SDRAMC peripheral ==========
AT91C_SDRAMC_ISR.name="AT91C_SDRAMC_ISR"
AT91C_SDRAMC_ISR.description="SDRAM Controller Interrupt Mask Register"
AT91C_SDRAMC_ISR.helpkey="SDRAM Controller Interrupt Mask Register"
AT91C_SDRAMC_ISR.access=memorymapped
AT91C_SDRAMC_ISR.address=0xFFFFEA20
AT91C_SDRAMC_ISR.width=32
AT91C_SDRAMC_ISR.byteEndian=little
AT91C_SDRAMC_ISR.permission.write=none
AT91C_SDRAMC_IDR.name="AT91C_SDRAMC_IDR"
AT91C_SDRAMC_IDR.description="SDRAM Controller Interrupt Disable Register"
AT91C_SDRAMC_IDR.helpkey="SDRAM Controller Interrupt Disable Register"
AT91C_SDRAMC_IDR.access=memorymapped
AT91C_SDRAMC_IDR.address=0xFFFFEA18
AT91C_SDRAMC_IDR.width=32
AT91C_SDRAMC_IDR.byteEndian=little
AT91C_SDRAMC_IDR.type=enum
AT91C_SDRAMC_IDR.enum.0.name=*** Write only ***
AT91C_SDRAMC_IDR.enum.1.name=Error
AT91C_SDRAMC_MR.name="AT91C_SDRAMC_MR"
AT91C_SDRAMC_MR.description="SDRAM Controller Mode Register"
AT91C_SDRAMC_MR.helpkey="SDRAM Controller Mode Register"
AT91C_SDRAMC_MR.access=memorymapped
AT91C_SDRAMC_MR.address=0xFFFFEA00
AT91C_SDRAMC_MR.width=32
AT91C_SDRAMC_MR.byteEndian=little
AT91C_SDRAMC_CR.name="AT91C_SDRAMC_CR"
AT91C_SDRAMC_CR.description="SDRAM Controller Configuration Register"
AT91C_SDRAMC_CR.helpkey="SDRAM Controller Configuration Register"
AT91C_SDRAMC_CR.access=memorymapped
AT91C_SDRAMC_CR.address=0xFFFFEA08
AT91C_SDRAMC_CR.width=32
AT91C_SDRAMC_CR.byteEndian=little
AT91C_SDRAMC_LPR.name="AT91C_SDRAMC_LPR"
AT91C_SDRAMC_LPR.description="SDRAM Controller Low Power Register"
AT91C_SDRAMC_LPR.helpkey="SDRAM Controller Low Power Register"
AT91C_SDRAMC_LPR.access=memorymapped
AT91C_SDRAMC_LPR.address=0xFFFFEA10
AT91C_SDRAMC_LPR.width=32
AT91C_SDRAMC_LPR.byteEndian=little
AT91C_SDRAMC_MDR.name="AT91C_SDRAMC_MDR"
AT91C_SDRAMC_MDR.description="SDRAM Memory Device Register"
AT91C_SDRAMC_MDR.helpkey="SDRAM Memory Device Register"
AT91C_SDRAMC_MDR.access=memorymapped
AT91C_SDRAMC_MDR.address=0xFFFFEA24
AT91C_SDRAMC_MDR.width=32
AT91C_SDRAMC_MDR.byteEndian=little
AT91C_SDRAMC_MDR.permission.write=none
AT91C_SDRAMC_TR.name="AT91C_SDRAMC_TR"
AT91C_SDRAMC_TR.description="SDRAM Controller Refresh Timer Register"
AT91C_SDRAMC_TR.helpkey="SDRAM Controller Refresh Timer Register"
AT91C_SDRAMC_TR.access=memorymapped
AT91C_SDRAMC_TR.address=0xFFFFEA04
AT91C_SDRAMC_TR.width=32
AT91C_SDRAMC_TR.byteEndian=little
AT91C_SDRAMC_HSR.name="AT91C_SDRAMC_HSR"
AT91C_SDRAMC_HSR.description="SDRAM Controller High Speed Register"
AT91C_SDRAMC_HSR.helpkey="SDRAM Controller High Speed Register"
AT91C_SDRAMC_HSR.access=memorymapped
AT91C_SDRAMC_HSR.address=0xFFFFEA0C
AT91C_SDRAMC_HSR.width=32
AT91C_SDRAMC_HSR.byteEndian=little
AT91C_SDRAMC_IER.name="AT91C_SDRAMC_IER"
AT91C_SDRAMC_IER.description="SDRAM Controller Interrupt Enable Register"
AT91C_SDRAMC_IER.helpkey="SDRAM Controller Interrupt Enable Register"
AT91C_SDRAMC_IER.access=memorymapped
AT91C_SDRAMC_IER.address=0xFFFFEA14
AT91C_SDRAMC_IER.width=32
AT91C_SDRAMC_IER.byteEndian=little
AT91C_SDRAMC_IER.type=enum
AT91C_SDRAMC_IER.enum.0.name=*** Write only ***
AT91C_SDRAMC_IER.enum.1.name=Error
AT91C_SDRAMC_IMR.name="AT91C_SDRAMC_IMR"
AT91C_SDRAMC_IMR.description="SDRAM Controller Interrupt Mask Register"
AT91C_SDRAMC_IMR.helpkey="SDRAM Controller Interrupt Mask Register"
AT91C_SDRAMC_IMR.access=memorymapped
AT91C_SDRAMC_IMR.address=0xFFFFEA1C
AT91C_SDRAMC_IMR.width=32
AT91C_SDRAMC_IMR.byteEndian=little
AT91C_SDRAMC_IMR.permission.write=none
# ========== Register definition for SMC peripheral ==========
AT91C_SMC_CYCLE1.name="AT91C_SMC_CYCLE1"
AT91C_SMC_CYCLE1.description=" Cycle Register for CS 1"
AT91C_SMC_CYCLE1.helpkey=" Cycle Register for CS 1"
AT91C_SMC_CYCLE1.access=memorymapped
AT91C_SMC_CYCLE1.address=0xFFFFEC18
AT91C_SMC_CYCLE1.width=32
AT91C_SMC_CYCLE1.byteEndian=little
AT91C_SMC_CTRL7.name="AT91C_SMC_CTRL7"
AT91C_SMC_CTRL7.description=" Control Register for CS 7"
AT91C_SMC_CTRL7.helpkey=" Control Register for CS 7"
AT91C_SMC_CTRL7.access=memorymapped
AT91C_SMC_CTRL7.address=0xFFFFEC7C
AT91C_SMC_CTRL7.width=32
AT91C_SMC_CTRL7.byteEndian=little
AT91C_SMC_CTRL2.name="AT91C_SMC_CTRL2"
AT91C_SMC_CTRL2.description=" Control Register for CS 2"
AT91C_SMC_CTRL2.helpkey=" Control Register for CS 2"
AT91C_SMC_CTRL2.access=memorymapped
AT91C_SMC_CTRL2.address=0xFFFFEC2C
AT91C_SMC_CTRL2.width=32
AT91C_SMC_CTRL2.byteEndian=little
AT91C_SMC_PULSE2.name="AT91C_SMC_PULSE2"
AT91C_SMC_PULSE2.description=" Pulse Register for CS 2"
AT91C_SMC_PULSE2.helpkey=" Pulse Register for CS 2"
AT91C_SMC_PULSE2.access=memorymapped
AT91C_SMC_PULSE2.address=0xFFFFEC24
AT91C_SMC_PULSE2.width=32
AT91C_SMC_PULSE2.byteEndian=little
AT91C_SMC_CTRL1.name="AT91C_SMC_CTRL1"
AT91C_SMC_CTRL1.description=" Control Register for CS 1"
AT91C_SMC_CTRL1.helpkey=" Control Register for CS 1"
AT91C_SMC_CTRL1.access=memorymapped
AT91C_SMC_CTRL1.address=0xFFFFEC1C
AT91C_SMC_CTRL1.width=32
AT91C_SMC_CTRL1.byteEndian=little
AT91C_SMC_SETUP4.name="AT91C_SMC_SETUP4"
AT91C_SMC_SETUP4.description=" Setup Register for CS 4"
AT91C_SMC_SETUP4.helpkey=" Setup Register for CS 4"
AT91C_SMC_SETUP4.access=memorymapped
AT91C_SMC_SETUP4.address=0xFFFFEC40
AT91C_SMC_SETUP4.width=32
AT91C_SMC_SETUP4.byteEndian=little
AT91C_SMC_CYCLE3.name="AT91C_SMC_CYCLE3"
AT91C_SMC_CYCLE3.description=" Cycle Register for CS 3"
AT91C_SMC_CYCLE3.helpkey=" Cycle Register for CS 3"
AT91C_SMC_CYCLE3.access=memorymapped
AT91C_SMC_CYCLE3.address=0xFFFFEC38
AT91C_SMC_CYCLE3.width=32
AT91C_SMC_CYCLE3.byteEndian=little
AT91C_SMC_SETUP3.name="AT91C_SMC_SETUP3"
AT91C_SMC_SETUP3.description=" Setup Register for CS 3"
AT91C_SMC_SETUP3.helpkey=" Setup Register for CS 3"
AT91C_SMC_SETUP3.access=memorymapped
AT91C_SMC_SETUP3.address=0xFFFFEC30
AT91C_SMC_SETUP3.width=32
AT91C_SMC_SETUP3.byteEndian=little
AT91C_SMC_CYCLE2.name="AT91C_SMC_CYCLE2"
AT91C_SMC_CYCLE2.description=" Cycle Register for CS 2"
AT91C_SMC_CYCLE2.helpkey=" Cycle Register for CS 2"
AT91C_SMC_CYCLE2.access=memorymapped
AT91C_SMC_CYCLE2.address=0xFFFFEC28
AT91C_SMC_CYCLE2.width=32
AT91C_SMC_CYCLE2.byteEndian=little
AT91C_SMC_SETUP2.name="AT91C_SMC_SETUP2"
AT91C_SMC_SETUP2.description=" Setup Register for CS 2"
AT91C_SMC_SETUP2.helpkey=" Setup Register for CS 2"
AT91C_SMC_SETUP2.access=memorymapped
AT91C_SMC_SETUP2.address=0xFFFFEC20
AT91C_SMC_SETUP2.width=32
AT91C_SMC_SETUP2.byteEndian=little
AT91C_SMC_PULSE5.name="AT91C_SMC_PULSE5"
AT91C_SMC_PULSE5.description=" Pulse Register for CS 5"
AT91C_SMC_PULSE5.helpkey=" Pulse Register for CS 5"
AT91C_SMC_PULSE5.access=memorymapped
AT91C_SMC_PULSE5.address=0xFFFFEC54
AT91C_SMC_PULSE5.width=32
AT91C_SMC_PULSE5.byteEndian=little
AT91C_SMC_CTRL4.name="AT91C_SMC_CTRL4"
AT91C_SMC_CTRL4.description=" Control Register for CS 4"
AT91C_SMC_CTRL4.helpkey=" Control Register for CS 4"
AT91C_SMC_CTRL4.access=memorymapped
AT91C_SMC_CTRL4.address=0xFFFFEC4C
AT91C_SMC_CTRL4.width=32
AT91C_SMC_CTRL4.byteEndian=little
AT91C_SMC_PULSE4.name="AT91C_SMC_PULSE4"
AT91C_SMC_PULSE4.description=" Pulse Register for CS 4"
AT91C_SMC_PULSE4.helpkey=" Pulse Register for CS 4"
AT91C_SMC_PULSE4.access=memorymapped
AT91C_SMC_PULSE4.address=0xFFFFEC44
AT91C_SMC_PULSE4.width=32
AT91C_SMC_PULSE4.byteEndian=little
AT91C_SMC_CTRL3.name="AT91C_SMC_CTRL3"
AT91C_SMC_CTRL3.description=" Control Register for CS 3"
AT91C_SMC_CTRL3.helpkey=" Control Register for CS 3"
AT91C_SMC_CTRL3.access=memorymapped
AT91C_SMC_CTRL3.address=0xFFFFEC3C
AT91C_SMC_CTRL3.width=32
AT91C_SMC_CTRL3.byteEndian=little
AT91C_SMC_PULSE3.name="AT91C_SMC_PULSE3"
AT91C_SMC_PULSE3.description=" Pulse Register for CS 3"
AT91C_SMC_PULSE3.helpkey=" Pulse Register for CS 3"
AT91C_SMC_PULSE3.access=memorymapped
AT91C_SMC_PULSE3.address=0xFFFFEC34
AT91C_SMC_PULSE3.width=32
AT91C_SMC_PULSE3.byteEndian=little
AT91C_SMC_PULSE0.name="AT91C_SMC_PULSE0"
AT91C_SMC_PULSE0.description=" Pulse Register for CS 0"
AT91C_SMC_PULSE0.helpkey=" Pulse Register for CS 0"
AT91C_SMC_PULSE0.access=memorymapped
AT91C_SMC_PULSE0.address=0xFFFFEC04
AT91C_SMC_PULSE0.width=32
AT91C_SMC_PULSE0.byteEndian=little
AT91C_SMC_CYCLE4.name="AT91C_SMC_CYCLE4"
AT91C_SMC_CYCLE4.description=" Cycle Register for CS 4"
AT91C_SMC_CYCLE4.helpkey=" Cycle Register for CS 4"
AT91C_SMC_CYCLE4.access=memorymapped
AT91C_SMC_CYCLE4.address=0xFFFFEC48
AT91C_SMC_CYCLE4.width=32
AT91C_SMC_CYCLE4.byteEndian=little
AT91C_SMC_SETUP5.name="AT91C_SMC_SETUP5"
AT91C_SMC_SETUP5.description=" Setup Register for CS 5"
AT91C_SMC_SETUP5.helpkey=" Setup Register for CS 5"
AT91C_SMC_SETUP5.access=memorymapped
AT91C_SMC_SETUP5.address=0xFFFFEC50
AT91C_SMC_SETUP5.width=32
AT91C_SMC_SETUP5.byteEndian=little
AT91C_SMC_CYCLE5.name="AT91C_SMC_CYCLE5"
AT91C_SMC_CYCLE5.description=" Cycle Register for CS 5"
AT91C_SMC_CYCLE5.helpkey=" Cycle Register for CS 5"
AT91C_SMC_CYCLE5.access=memorymapped
AT91C_SMC_CYCLE5.address=0xFFFFEC58
AT91C_SMC_CYCLE5.width=32
AT91C_SMC_CYCLE5.byteEndian=little
AT91C_SMC_SETUP6.name="AT91C_SMC_SETUP6"
AT91C_SMC_SETUP6.description=" Setup Register for CS 6"
AT91C_SMC_SETUP6.helpkey=" Setup Register for CS 6"
AT91C_SMC_SETUP6.access=memorymapped
AT91C_SMC_SETUP6.address=0xFFFFEC60
AT91C_SMC_SETUP6.width=32
AT91C_SMC_SETUP6.byteEndian=little
AT91C_SMC_CYCLE6.name="AT91C_SMC_CYCLE6"
AT91C_SMC_CYCLE6.description=" Cycle Register for CS 6"
AT91C_SMC_CYCLE6.helpkey=" Cycle Register for CS 6"
AT91C_SMC_CYCLE6.access=memorymapped
AT91C_SMC_CYCLE6.address=0xFFFFEC68
AT91C_SMC_CYCLE6.width=32
AT91C_SMC_CYCLE6.byteEndian=little
AT91C_SMC_SETUP0.name="AT91C_SMC_SETUP0"
AT91C_SMC_SETUP0.description=" Setup Register for CS 0"
AT91C_SMC_SETUP0.helpkey=" Setup Register for CS 0"
AT91C_SMC_SETUP0.access=memorymapped
AT91C_SMC_SETUP0.address=0xFFFFEC00
AT91C_SMC_SETUP0.width=32
AT91C_SMC_SETUP0.byteEndian=little
AT91C_SMC_CYCLE0.name="AT91C_SMC_CYCLE0"
AT91C_SMC_CYCLE0.description=" Cycle Register for CS 0"
AT91C_SMC_CYCLE0.helpkey=" Cycle Register for CS 0"
AT91C_SMC_CYCLE0.access=memorymapped
AT91C_SMC_CYCLE0.address=0xFFFFEC08
AT91C_SMC_CYCLE0.width=32
AT91C_SMC_CYCLE0.byteEndian=little
AT91C_SMC_SETUP1.name="AT91C_SMC_SETUP1"
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