📄 at91sam9261.inc
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;- -------- MATRIX_SCFG3 : (MATRIX Offset: 0x10) Slave Configuration Register 3 --------
AT91C_MATRIX_FIXED_DEFMSTR3 EQU (0x7:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_HPDC3 EQU (0x2:SHL:18) ;- (MATRIX) HPDC3 Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_LCDC EQU (0x3:SHL:18) ;- (MATRIX) LCDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR3_UHP EQU (0x4:SHL:18) ;- (MATRIX) UHP Master is Default Master
;- -------- MATRIX_SCFG4 : (MATRIX Offset: 0x14) Slave Configuration Register 4 --------
AT91C_MATRIX_FIXED_DEFMSTR4 EQU (0x3:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR4_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR4_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR4_HPDC3 EQU (0x2:SHL:18) ;- (MATRIX) HPDC3 Master is Default Master
;- -------- MATRIX_TCMR : (MATRIX Offset: 0x24) TCM (Slave 0) Special Function Register --------
AT91C_MATRIX_ITCM_SIZE EQU (0xF:SHL:0) ;- (MATRIX) Size of ITCM enabled memory block
AT91C_MATRIX_ITCM_SIZE_0KB EQU (0x0) ;- (MATRIX) 0 KB (No ITCM Memory)
AT91C_MATRIX_ITCM_SIZE_16KB EQU (0x5) ;- (MATRIX) 16 KB
AT91C_MATRIX_ITCM_SIZE_32KB EQU (0x6) ;- (MATRIX) 32 KB
AT91C_MATRIX_ITCM_SIZE_64KB EQU (0x7) ;- (MATRIX) 64 KB
AT91C_MATRIX_DTCM_SIZE EQU (0xF:SHL:4) ;- (MATRIX) Size of DTCM enabled memory block
AT91C_MATRIX_DTCM_SIZE_0KB EQU (0x0:SHL:4) ;- (MATRIX) 0 KB (No DTCM Memory)
AT91C_MATRIX_DTCM_SIZE_16KB EQU (0x5:SHL:4) ;- (MATRIX) 16 KB
AT91C_MATRIX_DTCM_SIZE_32KB EQU (0x6:SHL:4) ;- (MATRIX) 32 KB
AT91C_MATRIX_DTCM_SIZE_64KB EQU (0x7:SHL:4) ;- (MATRIX) 64 KB
;- -------- MATRIX_EBICSA : (MATRIX Offset: 0x30) EBI (Slave 3) Special Function Register --------
AT91C_MATRIX_CS1A EQU (0x1:SHL:1) ;- (MATRIX) Chip Select 1 Assignment
AT91C_MATRIX_CS1A_SMC EQU (0x0:SHL:1) ;- (MATRIX) Chip Select 1 is assigned to the Static Memory Controller.
AT91C_MATRIX_CS1A_SDRAMC EQU (0x1:SHL:1) ;- (MATRIX) Chip Select 1 is assigned to the SDRAM Controller.
AT91C_MATRIX_CS3A EQU (0x1:SHL:3) ;- (MATRIX) Chip Select 3 Assignment
AT91C_MATRIX_CS3A_SMC EQU (0x0:SHL:3) ;- (MATRIX) Chip Select 3 is only assigned to the Static Memory Controller and NCS3 behaves as defined by the SMC.
AT91C_MATRIX_CS3A_SM EQU (0x1:SHL:3) ;- (MATRIX) Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
AT91C_MATRIX_CS4A EQU (0x1:SHL:4) ;- (MATRIX) Chip Select 4 Assignment
AT91C_MATRIX_CS4A_SMC EQU (0x0:SHL:4) ;- (MATRIX) Chip Select 4 is only assigned to the Static Memory Controller and NCS4 behaves as defined by the SMC.
AT91C_MATRIX_CS4A_CF EQU (0x1:SHL:4) ;- (MATRIX) Chip Select 4 is assigned to the Static Memory Controller and the CompactFlash Logic (first slot) is activated.
AT91C_MATRIX_CS5A EQU (0x1:SHL:5) ;- (MATRIX) Chip Select 5 Assignment
AT91C_MATRIX_CS5A_SMC EQU (0x0:SHL:5) ;- (MATRIX) Chip Select 5 is only assigned to the Static Memory Controller and NCS5 behaves as defined by the SMC
AT91C_MATRIX_CS5A_CF EQU (0x1:SHL:5) ;- (MATRIX) Chip Select 5 is assigned to the Static Memory Controller and the CompactFlash Logic (second slot) is activated.
AT91C_MATRIX_DBPUC EQU (0x1:SHL:8) ;- (MATRIX) Data Bus Pull-up Configuration
;- -------- MATRIX_USBPCR : (MATRIX Offset: 0x34) USB Pad Control Register --------
AT91C_MATRIX_USBPCR_PUON EQU (0x1:SHL:30) ;- (MATRIX) PullUp On
AT91C_MATRIX_USBPCR_PUIDLE EQU (0x1:SHL:31) ;- (MATRIX) PullUp Idle
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Advanced Interrupt Controller
;- *****************************************************************************
^ 0 ;- AT91S_AIC
AIC_SMR # 128 ;- Source Mode Register
AIC_SVR # 128 ;- Source Vector Register
AIC_IVR # 4 ;- IRQ Vector Register
AIC_FVR # 4 ;- FIQ Vector Register
AIC_ISR # 4 ;- Interrupt Status Register
AIC_IPR # 4 ;- Interrupt Pending Register
AIC_IMR # 4 ;- Interrupt Mask Register
AIC_CISR # 4 ;- Core Interrupt Status Register
# 8 ;- Reserved
AIC_IECR # 4 ;- Interrupt Enable Command Register
AIC_IDCR # 4 ;- Interrupt Disable Command Register
AIC_ICCR # 4 ;- Interrupt Clear Command Register
AIC_ISCR # 4 ;- Interrupt Set Command Register
AIC_EOICR # 4 ;- End of Interrupt Command Register
AIC_SPU # 4 ;- Spurious Vector Register
AIC_DCR # 4 ;- Debug Control Register (Protect)
# 4 ;- Reserved
AIC_FFER # 4 ;- Fast Forcing Enable Register
AIC_FFDR # 4 ;- Fast Forcing Disable Register
AIC_FFSR # 4 ;- Fast Forcing Status Register
;- -------- AIC_SMR : (AIC Offset: 0x0) Control Register --------
AT91C_AIC_PRIOR EQU (0x7:SHL:0) ;- (AIC) Priority Level
AT91C_AIC_PRIOR_LOWEST EQU (0x0) ;- (AIC) Lowest priority level
AT91C_AIC_PRIOR_HIGHEST EQU (0x7) ;- (AIC) Highest priority level
AT91C_AIC_SRCTYPE EQU (0x3:SHL:5) ;- (AIC) Interrupt Source Type
AT91C_AIC_SRCTYPE_INT_LEVEL_SENSITIVE EQU (0x0:SHL:5) ;- (AIC) Internal Sources Code Label Level Sensitive
AT91C_AIC_SRCTYPE_INT_EDGE_TRIGGERED EQU (0x1:SHL:5) ;- (AIC) Internal Sources Code Label Edge triggered
AT91C_AIC_SRCTYPE_EXT_HIGH_LEVEL EQU (0x2:SHL:5) ;- (AIC) External Sources Code Label High-level Sensitive
AT91C_AIC_SRCTYPE_EXT_POSITIVE_EDGE EQU (0x3:SHL:5) ;- (AIC) External Sources Code Label Positive Edge triggered
;- -------- AIC_CISR : (AIC Offset: 0x114) AIC Core Interrupt Status Register --------
AT91C_AIC_NFIQ EQU (0x1:SHL:0) ;- (AIC) NFIQ Status
AT91C_AIC_NIRQ EQU (0x1:SHL:1) ;- (AIC) NIRQ Status
;- -------- AIC_DCR : (AIC Offset: 0x138) AIC Debug Control Register (Protect) --------
AT91C_AIC_DCR_PROT EQU (0x1:SHL:0) ;- (AIC) Protection Mode
AT91C_AIC_DCR_GMSK EQU (0x1:SHL:1) ;- (AIC) General Mask
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Peripheral DMA Controller
;- *****************************************************************************
^ 0 ;- AT91S_PDC
PDC_RPR # 4 ;- Receive Pointer Register
PDC_RCR # 4 ;- Receive Counter Register
PDC_TPR # 4 ;- Transmit Pointer Register
PDC_TCR # 4 ;- Transmit Counter Register
PDC_RNPR # 4 ;- Receive Next Pointer Register
PDC_RNCR # 4 ;- Receive Next Counter Register
PDC_TNPR # 4 ;- Transmit Next Pointer Register
PDC_TNCR # 4 ;- Transmit Next Counter Register
PDC_PTCR # 4 ;- PDC Transfer Control Register
PDC_PTSR # 4 ;- PDC Transfer Status Register
;- -------- PDC_PTCR : (PDC Offset: 0x20) PDC Transfer Control Register --------
AT91C_PDC_RXTEN EQU (0x1:SHL:0) ;- (PDC) Receiver Transfer Enable
AT91C_PDC_RXTDIS EQU (0x1:SHL:1) ;- (PDC) Receiver Transfer Disable
AT91C_PDC_TXTEN EQU (0x1:SHL:8) ;- (PDC) Transmitter Transfer Enable
AT91C_PDC_TXTDIS EQU (0x1:SHL:9) ;- (PDC) Transmitter Transfer Disable
;- -------- PDC_PTSR : (PDC Offset: 0x24) PDC Transfer Status Register --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Debug Unit
;- *****************************************************************************
^ 0 ;- AT91S_DBGU
DBGU_CR # 4 ;- Control Register
DBGU_MR # 4 ;- Mode Register
DBGU_IER # 4 ;- Interrupt Enable Register
DBGU_IDR # 4 ;- Interrupt Disable Register
DBGU_IMR # 4 ;- Interrupt Mask Register
DBGU_CSR # 4 ;- Channel Status Register
DBGU_RHR # 4 ;- Receiver Holding Register
DBGU_THR # 4 ;- Transmitter Holding Register
DBGU_BRGR # 4 ;- Baud Rate Generator Register
# 28 ;- Reserved
DBGU_CIDR # 4 ;- Chip ID Register
DBGU_EXID # 4 ;- Chip ID Extension Register
DBGU_FNTR # 4 ;- Force NTRST Register
# 180 ;- Reserved
DBGU_RPR # 4 ;- Receive Pointer Register
DBGU_RCR # 4 ;- Receive Counter Register
DBGU_TPR # 4 ;- Transmit Pointer Register
DBGU_TCR # 4 ;- Transmit Counter Register
DBGU_RNPR # 4 ;- Receive Next Pointer Register
DBGU_RNCR # 4 ;- Receive Next Counter Register
DBGU_TNPR # 4 ;- Transmit Next Pointer Register
DBGU_TNCR # 4 ;- Transmit Next Counter Register
DBGU_PTCR # 4 ;- PDC Transfer Control Register
DBGU_PTSR # 4 ;- PDC Transfer Status Register
;- -------- DBGU_CR : (DBGU Offset: 0x0) Debug Unit Control Register --------
AT91C_US_RSTRX EQU (0x1:SHL:2) ;- (DBGU) Reset Receiver
AT91C_US_RSTTX EQU (0x1:SHL:3) ;- (DBGU) Reset Transmitter
AT91C_US_RXEN EQU (0x1:SHL:4) ;- (DBGU) Receiver Enable
AT91C_US_RXDIS EQU (0x1:SHL:5) ;- (DBGU) Receiver Disable
AT91C_US_TXEN EQU (0x1:SHL:6) ;- (DBGU) Transmitter Enable
AT91C_US_TXDIS EQU (0x1:SHL:7) ;- (DBGU) Transmitter Disable
AT91C_US_RSTSTA EQU (0x1:SHL:8) ;- (DBGU) Reset Status Bits
;- -------- DBGU_MR : (DBGU Offset: 0x4) Debug Unit Mode Register --------
AT91C_US_PAR EQU (0x7:SHL:9) ;- (DBGU) Parity type
AT91C_US_PAR_EVEN EQU (0x0:SHL:9) ;- (DBGU) Even Parity
AT91C_US_PAR_ODD EQU (0x1:SHL:9) ;- (DBGU) Odd Parity
AT91C_US_PAR_SPACE EQU (0x2:SHL:9) ;- (DBGU) Parity forced to 0 (Space)
AT91C_US_PAR_MARK EQU (0x3:SHL:9) ;- (DBGU) Parity forced to 1 (Mark)
AT91C_US_PAR_NONE EQU (0x4:SHL:9) ;- (DBGU) No Parity
AT91C_US_PAR_MULTI_DROP EQU (0x6:SHL:9) ;- (DBGU) Multi-drop mode
AT91C_US_CHMODE EQU (0x3:SHL:14) ;- (DBGU) Channel Mode
AT91C_US_CHMODE_NORMAL EQU (0x0:SHL:14) ;- (DBGU) Normal Mode: The USART channel operates as an RX/TX USART.
AT91C_US_CHMODE_AUTO EQU (0x1:SHL:14) ;- (DBGU) Automatic Echo: Receiver Data Input is connected to the TXD pin.
AT91C_US_CHMODE_LOCAL EQU (0x2:SHL:14) ;- (DBGU) Local Loopback: Transmitter Output Signal is connected to Receiver Input Signal.
AT91C_US_CHMODE_REMOTE EQU (0x3:SHL:14) ;- (DBGU) Remote Loopback: RXD pin is internally connected to TXD pin.
;- -------- DBGU_IER : (DBGU Offset: 0x8) Debug Unit Interrupt Enable Register --------
AT91C_US_RXRDY EQU (0x1:SHL:0) ;- (DBGU) RXRDY Interrupt
AT91C_US_TXRDY EQU (0x1:SHL:1) ;- (DBGU) TXRDY Interrupt
AT91C_US_ENDRX EQU (0x1:SHL:3) ;- (DBGU) End of Receive Transfer Interrupt
AT91C_US_ENDTX EQU (0x1:SHL:4) ;- (DBGU) End of Transmit Interrupt
AT91C_US_OVRE EQU (0x1:SHL:5) ;- (DBGU) Overrun Interrupt
AT91C_US_FRAME EQU (0x1:SHL:6) ;- (DBGU) Framing Error Interrupt
AT91C_US_PARE EQU (0x1:SHL:7) ;- (DBGU) Parity Error Interrupt
AT91C_US_TXEMPTY EQU (0x1:SHL:9) ;- (DBGU) TXEMPTY Interrupt
AT91C_US_TXBUFE EQU (0x1:SHL:11) ;- (DBGU) TXBUFE Interrupt
AT91C_US_RXBUFF EQU (0x1:SHL:12) ;- (DBGU) RXBUFF Interrupt
AT91C_US_COMM_TX EQU (0x1:SHL:30) ;- (DBGU) COMM_TX Interrupt
AT91C_US_COMM_RX EQU (0x1:SHL:31) ;- (DBGU) COMM_RX Interrupt
;- -------- DBGU_IDR : (DBGU Offset: 0xc) Debug Unit Interrupt Disable Register --------
;- -------- DBGU_IMR : (DBGU Offset: 0x10) Debug Unit Interrupt Mask Register --------
;- -------- DBGU_CSR : (DBGU Offset: 0x14) Debug Unit Channel Status Register --------
;- -------- DBGU_FNTR : (DBGU Offset: 0x48) Debug Unit FORCE_NTRST Register --------
AT91C_US_FORCE_NTRST EQU (0x1:SHL:0) ;- (DBGU) Force NTRST in JTAG
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Parallel Input Output Controler
;- *****************************************************************************
^ 0 ;- AT91S_PIO
PIO_PER # 4 ;- PIO Enable Register
PIO_PDR # 4 ;- PIO Disable Register
PIO_PSR # 4 ;- PIO Status Register
# 4 ;- Reserved
PIO_OER # 4 ;- Output Enable Register
PIO_ODR # 4 ;- Output Disable Registerr
PIO_OSR # 4 ;- Output Status Register
# 4 ;- Reserved
PIO_IFER # 4 ;- Input Filter Enable Register
PIO_IFDR # 4 ;- Input Filter Disable Register
PIO_IFSR # 4 ;- Input Filter Status Register
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