📄 at91sam9261.inc
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AT91C_SDRAMC_TXSR_1 EQU (0x1:SHL:28) ;- (SDRAMC) Value : 1
AT91C_SDRAMC_TXSR_2 EQU (0x2:SHL:28) ;- (SDRAMC) Value : 2
AT91C_SDRAMC_TXSR_3 EQU (0x3:SHL:28) ;- (SDRAMC) Value : 3
AT91C_SDRAMC_TXSR_4 EQU (0x4:SHL:28) ;- (SDRAMC) Value : 4
AT91C_SDRAMC_TXSR_5 EQU (0x5:SHL:28) ;- (SDRAMC) Value : 5
AT91C_SDRAMC_TXSR_6 EQU (0x6:SHL:28) ;- (SDRAMC) Value : 6
AT91C_SDRAMC_TXSR_7 EQU (0x7:SHL:28) ;- (SDRAMC) Value : 7
AT91C_SDRAMC_TXSR_8 EQU (0x8:SHL:28) ;- (SDRAMC) Value : 8
AT91C_SDRAMC_TXSR_9 EQU (0x9:SHL:28) ;- (SDRAMC) Value : 9
AT91C_SDRAMC_TXSR_10 EQU (0xA:SHL:28) ;- (SDRAMC) Value : 10
AT91C_SDRAMC_TXSR_11 EQU (0xB:SHL:28) ;- (SDRAMC) Value : 11
AT91C_SDRAMC_TXSR_12 EQU (0xC:SHL:28) ;- (SDRAMC) Value : 12
AT91C_SDRAMC_TXSR_13 EQU (0xD:SHL:28) ;- (SDRAMC) Value : 13
AT91C_SDRAMC_TXSR_14 EQU (0xE:SHL:28) ;- (SDRAMC) Value : 14
AT91C_SDRAMC_TXSR_15 EQU (0xF:SHL:28) ;- (SDRAMC) Value : 15
;- -------- SDRAMC_HSR : (SDRAMC Offset: 0xc) SDRAM Controller High Speed Register --------
AT91C_SDRAMC_DA EQU (0x1:SHL:0) ;- (SDRAMC) Decode Cycle Enable Bit
AT91C_SDRAMC_DA_DISABLE EQU (0x0) ;- (SDRAMC) Disable Decode Cycle
AT91C_SDRAMC_DA_ENABLE EQU (0x1) ;- (SDRAMC) Enable Decode Cycle
;- -------- SDRAMC_LPR : (SDRAMC Offset: 0x10) SDRAM Controller Low-power Register --------
AT91C_SDRAMC_LPCB EQU (0x3:SHL:0) ;- (SDRAMC) Low-power Configurations
AT91C_SDRAMC_LPCB_DISABLE EQU (0x0) ;- (SDRAMC) Disable Low Power Features
AT91C_SDRAMC_LPCB_SELF_REFRESH EQU (0x1) ;- (SDRAMC) Enable SELF_REFRESH
AT91C_SDRAMC_LPCB_POWER_DOWN EQU (0x2) ;- (SDRAMC) Enable POWER_DOWN
AT91C_SDRAMC_LPCB_DEEP_POWER_DOWN EQU (0x3) ;- (SDRAMC) Enable DEEP_POWER_DOWN
AT91C_SDRAMC_PASR EQU (0x7:SHL:4) ;- (SDRAMC) Partial Array Self Refresh (only for Low Power SDRAM)
AT91C_SDRAMC_TCSR EQU (0x3:SHL:8) ;- (SDRAMC) Temperature Compensated Self Refresh (only for Low Power SDRAM)
AT91C_SDRAMC_DS EQU (0x3:SHL:10) ;- (SDRAMC) Drive Strenght (only for Low Power SDRAM)
AT91C_SDRAMC_TIMEOUT EQU (0x3:SHL:12) ;- (SDRAMC) Time to define when Low Power Mode is enabled
AT91C_SDRAMC_TIMEOUT_0_CLK_CYCLES EQU (0x0:SHL:12) ;- (SDRAMC) Activate SDRAM Low Power Mode Immediately
AT91C_SDRAMC_TIMEOUT_64_CLK_CYCLES EQU (0x1:SHL:12) ;- (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
AT91C_SDRAMC_TIMEOUT_128_CLK_CYCLES EQU (0x2:SHL:12) ;- (SDRAMC) Activate SDRAM Low Power Mode after 64 clock cycles after the end of the last transfer
;- -------- SDRAMC_IER : (SDRAMC Offset: 0x14) SDRAM Controller Interrupt Enable Register --------
AT91C_SDRAMC_RES EQU (0x1:SHL:0) ;- (SDRAMC) Refresh Error Status
;- -------- SDRAMC_IDR : (SDRAMC Offset: 0x18) SDRAM Controller Interrupt Disable Register --------
;- -------- SDRAMC_IMR : (SDRAMC Offset: 0x1c) SDRAM Controller Interrupt Mask Register --------
;- -------- SDRAMC_ISR : (SDRAMC Offset: 0x20) SDRAM Controller Interrupt Status Register --------
;- -------- SDRAMC_MDR : (SDRAMC Offset: 0x24) SDRAM Controller Memory Device Register --------
AT91C_SDRAMC_MD EQU (0x3:SHL:0) ;- (SDRAMC) Memory Device Type
AT91C_SDRAMC_MD_SDRAM EQU (0x0) ;- (SDRAMC) SDRAM Mode
AT91C_SDRAMC_MD_LOW_POWER_SDRAM EQU (0x1) ;- (SDRAMC) SDRAM Low Power Mode
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR Static Memory Controller Interface
;- *****************************************************************************
^ 0 ;- AT91S_SMC
SMC_SETUP0 # 4 ;- Setup Register for CS 0
SMC_PULSE0 # 4 ;- Pulse Register for CS 0
SMC_CYCLE0 # 4 ;- Cycle Register for CS 0
SMC_CTRL0 # 4 ;- Control Register for CS 0
SMC_SETUP1 # 4 ;- Setup Register for CS 1
SMC_PULSE1 # 4 ;- Pulse Register for CS 1
SMC_CYCLE1 # 4 ;- Cycle Register for CS 1
SMC_CTRL1 # 4 ;- Control Register for CS 1
SMC_SETUP2 # 4 ;- Setup Register for CS 2
SMC_PULSE2 # 4 ;- Pulse Register for CS 2
SMC_CYCLE2 # 4 ;- Cycle Register for CS 2
SMC_CTRL2 # 4 ;- Control Register for CS 2
SMC_SETUP3 # 4 ;- Setup Register for CS 3
SMC_PULSE3 # 4 ;- Pulse Register for CS 3
SMC_CYCLE3 # 4 ;- Cycle Register for CS 3
SMC_CTRL3 # 4 ;- Control Register for CS 3
SMC_SETUP4 # 4 ;- Setup Register for CS 4
SMC_PULSE4 # 4 ;- Pulse Register for CS 4
SMC_CYCLE4 # 4 ;- Cycle Register for CS 4
SMC_CTRL4 # 4 ;- Control Register for CS 4
SMC_SETUP5 # 4 ;- Setup Register for CS 5
SMC_PULSE5 # 4 ;- Pulse Register for CS 5
SMC_CYCLE5 # 4 ;- Cycle Register for CS 5
SMC_CTRL5 # 4 ;- Control Register for CS 5
SMC_SETUP6 # 4 ;- Setup Register for CS 6
SMC_PULSE6 # 4 ;- Pulse Register for CS 6
SMC_CYCLE6 # 4 ;- Cycle Register for CS 6
SMC_CTRL6 # 4 ;- Control Register for CS 6
SMC_SETUP7 # 4 ;- Setup Register for CS 7
SMC_PULSE7 # 4 ;- Pulse Register for CS 7
SMC_CYCLE7 # 4 ;- Cycle Register for CS 7
SMC_CTRL7 # 4 ;- Control Register for CS 7
;- -------- SMC_SETUP : (SMC Offset: 0x0) Setup Register for CS x --------
AT91C_SMC_NWESETUP EQU (0x3F:SHL:0) ;- (SMC) NWE Setup Length
AT91C_SMC_NCSSETUPWR EQU (0x3F:SHL:8) ;- (SMC) NCS Setup Length in WRite Access
AT91C_SMC_NRDSETUP EQU (0x3F:SHL:16) ;- (SMC) NRD Setup Length
AT91C_SMC_NCSSETUPRD EQU (0x3F:SHL:24) ;- (SMC) NCS Setup Length in ReaD Access
;- -------- SMC_PULSE : (SMC Offset: 0x4) Pulse Register for CS x --------
AT91C_SMC_NWEPULSE EQU (0x7F:SHL:0) ;- (SMC) NWE Pulse Length
AT91C_SMC_NCSPULSEWR EQU (0x7F:SHL:8) ;- (SMC) NCS Pulse Length in WRite Access
AT91C_SMC_NRDPULSE EQU (0x7F:SHL:16) ;- (SMC) NRD Pulse Length
AT91C_SMC_NCSPULSERD EQU (0x7F:SHL:24) ;- (SMC) NCS Pulse Length in ReaD Access
;- -------- SMC_CYC : (SMC Offset: 0x8) Cycle Register for CS x --------
AT91C_SMC_NWECYCLE EQU (0x1FF:SHL:0) ;- (SMC) Total Write Cycle Length
AT91C_SMC_NRDCYCLE EQU (0x1FF:SHL:16) ;- (SMC) Total Read Cycle Length
;- -------- SMC_CTRL : (SMC Offset: 0xc) Control Register for CS x --------
AT91C_SMC_READMODE EQU (0x1:SHL:0) ;- (SMC) Read Mode
AT91C_SMC_WRITEMODE EQU (0x1:SHL:1) ;- (SMC) Write Mode
AT91C_SMC_NWAITM EQU (0x3:SHL:5) ;- (SMC) NWAIT Mode
AT91C_SMC_NWAITM_NWAIT_DISABLE EQU (0x0:SHL:5) ;- (SMC) External NWAIT disabled.
AT91C_SMC_NWAITM_NWAIT_ENABLE_FROZEN EQU (0x2:SHL:5) ;- (SMC) External NWAIT enabled in frozen mode.
AT91C_SMC_NWAITM_NWAIT_ENABLE_READY EQU (0x3:SHL:5) ;- (SMC) External NWAIT enabled in ready mode.
AT91C_SMC_BAT EQU (0x1:SHL:8) ;- (SMC) Byte Access Type
AT91C_SMC_BAT_BYTE_SELECT EQU (0x0:SHL:8) ;- (SMC) Write controled by ncs, nbs0, nbs1, nbs2, nbs3. Read controled by ncs, nrd, nbs0, nbs1, nbs2, nbs3.
AT91C_SMC_BAT_BYTE_WRITE EQU (0x1:SHL:8) ;- (SMC) Write controled by ncs, nwe0, nwe1, nwe2, nwe3. Read controled by ncs and nrd.
AT91C_SMC_DBW EQU (0x3:SHL:12) ;- (SMC) Data Bus Width
AT91C_SMC_DBW_WIDTH_EIGTH_BITS EQU (0x0:SHL:12) ;- (SMC) 8 bits.
AT91C_SMC_DBW_WIDTH_SIXTEEN_BITS EQU (0x1:SHL:12) ;- (SMC) 16 bits.
AT91C_SMC_DBW_WIDTH_THIRTY_TWO_BITS EQU (0x2:SHL:12) ;- (SMC) 32 bits.
AT91C_SMC_TDF EQU (0xF:SHL:16) ;- (SMC) Data Float Time.
AT91C_SMC_TDFEN EQU (0x1:SHL:20) ;- (SMC) TDF Enabled.
AT91C_SMC_PMEN EQU (0x1:SHL:24) ;- (SMC) Page Mode Enabled.
AT91C_SMC_PS EQU (0x3:SHL:28) ;- (SMC) Page Size
AT91C_SMC_PS_SIZE_FOUR_BYTES EQU (0x0:SHL:28) ;- (SMC) 4 bytes.
AT91C_SMC_PS_SIZE_EIGHT_BYTES EQU (0x1:SHL:28) ;- (SMC) 8 bytes.
AT91C_SMC_PS_SIZE_SIXTEEN_BYTES EQU (0x2:SHL:28) ;- (SMC) 16 bytes.
AT91C_SMC_PS_SIZE_THIRTY_TWO_BYTES EQU (0x3:SHL:28) ;- (SMC) 32 bytes.
;- -------- SMC_SETUP : (SMC Offset: 0x10) Setup Register for CS x --------
;- -------- SMC_PULSE : (SMC Offset: 0x14) Pulse Register for CS x --------
;- -------- SMC_CYC : (SMC Offset: 0x18) Cycle Register for CS x --------
;- -------- SMC_CTRL : (SMC Offset: 0x1c) Control Register for CS x --------
;- -------- SMC_SETUP : (SMC Offset: 0x20) Setup Register for CS x --------
;- -------- SMC_PULSE : (SMC Offset: 0x24) Pulse Register for CS x --------
;- -------- SMC_CYC : (SMC Offset: 0x28) Cycle Register for CS x --------
;- -------- SMC_CTRL : (SMC Offset: 0x2c) Control Register for CS x --------
;- -------- SMC_SETUP : (SMC Offset: 0x30) Setup Register for CS x --------
;- -------- SMC_PULSE : (SMC Offset: 0x34) Pulse Register for CS x --------
;- -------- SMC_CYC : (SMC Offset: 0x38) Cycle Register for CS x --------
;- -------- SMC_CTRL : (SMC Offset: 0x3c) Control Register for CS x --------
;- -------- SMC_SETUP : (SMC Offset: 0x40) Setup Register for CS x --------
;- -------- SMC_PULSE : (SMC Offset: 0x44) Pulse Register for CS x --------
;- -------- SMC_CYC : (SMC Offset: 0x48) Cycle Register for CS x --------
;- -------- SMC_CTRL : (SMC Offset: 0x4c) Control Register for CS x --------
;- -------- SMC_SETUP : (SMC Offset: 0x50) Setup Register for CS x --------
;- -------- SMC_PULSE : (SMC Offset: 0x54) Pulse Register for CS x --------
;- -------- SMC_CYC : (SMC Offset: 0x58) Cycle Register for CS x --------
;- -------- SMC_CTRL : (SMC Offset: 0x5c) Control Register for CS x --------
;- -------- SMC_SETUP : (SMC Offset: 0x60) Setup Register for CS x --------
;- -------- SMC_PULSE : (SMC Offset: 0x64) Pulse Register for CS x --------
;- -------- SMC_CYC : (SMC Offset: 0x68) Cycle Register for CS x --------
;- -------- SMC_CTRL : (SMC Offset: 0x6c) Control Register for CS x --------
;- -------- SMC_SETUP : (SMC Offset: 0x70) Setup Register for CS x --------
;- -------- SMC_PULSE : (SMC Offset: 0x74) Pulse Register for CS x --------
;- -------- SMC_CYC : (SMC Offset: 0x78) Cycle Register for CS x --------
;- -------- SMC_CTRL : (SMC Offset: 0x7c) Control Register for CS x --------
;- *****************************************************************************
;- SOFTWARE API DEFINITION FOR AHB Matrix Interface
;- *****************************************************************************
^ 0 ;- AT91S_MATRIX
MATRIX_MCFG # 4 ;- Master Configuration Register
MATRIX_SCFG0 # 4 ;- Slave Configuration Register 0
MATRIX_SCFG1 # 4 ;- Slave Configuration Register 1
MATRIX_SCFG2 # 4 ;- Slave Configuration Register 2
MATRIX_SCFG3 # 4 ;- Slave Configuration Register 3
MATRIX_SCFG4 # 4 ;- Slave Configuration Register 4
# 12 ;- Reserved
MATRIX_TCMR # 4 ;- Slave 0 Special Function Register
# 8 ;- Reserved
MATRIX_EBICSA # 4 ;- Slave 3 Special Function Register
MATRIX_USBPCR # 4 ;- Slave 4 Special Function Register
# 12 ;- Reserved
MATRIX_VERSION # 4 ;- Version Register
;- -------- MATRIX_MCFG : (MATRIX Offset: 0x0) Master Configuration Register --------
AT91C_MATRIX_RCA926I EQU (0x1:SHL:0) ;- (MATRIX) Remap Command for ARM926EJ-S Instruction Master
AT91C_MATRIX_RCA926D EQU (0x1:SHL:1) ;- (MATRIX) Remap Command for ARM926EJ-S Data Master
;- -------- MATRIX_SCFG0 : (MATRIX Offset: 0x4) Slave Configuration Register 0 --------
AT91C_MATRIX_SLOT_CYCLE EQU (0xFF:SHL:0) ;- (MATRIX) Maximum Number of Allowed Cycles for a Burst
AT91C_MATRIX_DEFMSTR_TYPE EQU (0x3:SHL:16) ;- (MATRIX) Default Master Type
AT91C_MATRIX_DEFMSTR_TYPE_NO_DEFMSTR EQU (0x0:SHL:16) ;- (MATRIX) No Default Master. At the end of current slave access, if no other master request is pending, the slave is deconnected from all masters. This results in having a one cycle latency for the first transfer of a burst.
AT91C_MATRIX_DEFMSTR_TYPE_LAST_DEFMSTR EQU (0x1:SHL:16) ;- (MATRIX) Last Default Master. At the end of current slave access, if no other master request is pending, the slave stay connected with the last master having accessed it. This results in not having the one cycle latency when the last master re-trying access on the slave.
AT91C_MATRIX_DEFMSTR_TYPE_FIXED_DEFMSTR EQU (0x2:SHL:16) ;- (MATRIX) Fixed Default Master. At the end of current slave access, if no other master request is pending, the slave connects with fixed which number is in FIXED_DEFMSTR field. This results in not having the one cycle latency when the fixed master re-trying access on the slave.
AT91C_MATRIX_FIXED_DEFMSTR0 EQU (0x7:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_HPDC3 EQU (0x2:SHL:18) ;- (MATRIX) HPDC3 Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_LCDC EQU (0x3:SHL:18) ;- (MATRIX) LCDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR0_UHP EQU (0x4:SHL:18) ;- (MATRIX) UHP Master is Default Master
;- -------- MATRIX_SCFG1 : (MATRIX Offset: 0x8) Slave Configuration Register 1 --------
AT91C_MATRIX_FIXED_DEFMSTR1 EQU (0x7:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_HPDC3 EQU (0x2:SHL:18) ;- (MATRIX) HPDC3 Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_LCDC EQU (0x3:SHL:18) ;- (MATRIX) LCDC Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR1_UHP EQU (0x4:SHL:18) ;- (MATRIX) UHP Master is Default Master
;- -------- MATRIX_SCFG2 : (MATRIX Offset: 0xc) Slave Configuration Register 2 --------
AT91C_MATRIX_FIXED_DEFMSTR2 EQU (0x1:SHL:18) ;- (MATRIX) Fixed Index of Default Master
AT91C_MATRIX_FIXED_DEFMSTR2_ARM926I EQU (0x0:SHL:18) ;- (MATRIX) ARM926EJ-S Instruction Master is Default Master
AT91C_MATRIX_FIXED_DEFMSTR2_ARM926D EQU (0x1:SHL:18) ;- (MATRIX) ARM926EJ-S Data Master is Default Master
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