at91sam9261.inc

AT91SAM 系列微控制器的NAND Flash支持代码 描述怎样将NAND Flash和AT91SAM 系列微控制器连接起来。

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;- File Name           : AT91SAM9261.h
;- Object              : AT91SAM9261 definitions
;- Generated           : AT91 SW Application Group  09/12/2005 (15:39:28)
;- 
;- CVS Reference       : /AT91SAM9261.pl/1.12/Mon Sep 12 13:26:48 2005//
;- CVS Reference       : /SYS_SAM9261.pl/1.5/Thu Nov 18 13:22:33 2004//
;- CVS Reference       : /HMATRIX1_SAM9261.pl/1.2/Mon Nov  8 16:38:17 2004//
;- CVS Reference       : /PMC_SAM9261.pl/1.4/Fri Sep  9 15:24:01 2005//
;- CVS Reference       : /HSMC3_SAM9261.pl/1.1/Tue Nov 16 09:16:07 2004//
;- CVS Reference       : /SHDWC_SAM9261.pl/1.1/Tue Mar  8 14:46:52 2005//
;- CVS Reference       : /UDP_SAM9261.pl/1.1/Tue May 10 12:39:24 2005//
;- CVS Reference       : /HSDRAMC1_6100A.pl/1.2/Mon Aug  9 10:52:25 2004//
;- CVS Reference       : /AIC_6075B.pl/1.3/Fri May 20 14:21:42 2005//
;- CVS Reference       : /PDC_6074C.pl/1.2/Thu Feb  3 09:02:11 2005//
;- CVS Reference       : /DBGU_6059D.pl/1.1/Mon Jan 31 13:54:41 2005//
;- CVS Reference       : /PIO_6057A.pl/1.2/Thu Feb  3 10:29:42 2005//
;- CVS Reference       : /RSTC_6098A.pl/1.3/Thu Nov  4 13:57:00 2004//
;- CVS Reference       : /RTTC_6081A.pl/1.2/Thu Nov  4 13:57:22 2004//
;- CVS Reference       : /PITC_6079A.pl/1.2/Thu Nov  4 13:56:22 2004//
;- CVS Reference       : /WDTC_6080A.pl/1.3/Thu Nov  4 13:58:52 2004//
;- CVS Reference       : /TC_6082A.pl/1.7/Wed Mar  9 16:31:51 2005//
;- CVS Reference       : /MCI_6101A.pl/1.1/Tue Jul 13 06:33:59 2004//
;- CVS Reference       : /TWI_6061A.pl/1.1/Tue Jul 13 06:38:23 2004//
;- CVS Reference       : /US_6089C.pl/1.1/Mon Jan 31 13:56:02 2005//
;- CVS Reference       : /SSC_6078B.pl/1.1/Wed Jul 13 15:25:46 2005//
;- CVS Reference       : /SPI_6088D.pl/1.3/Fri May 20 14:23:02 2005//
;- CVS Reference       : /UHP_6127A.pl/1.1/Wed Feb 23 16:03:17 2005//
;- CVS Reference       : /LCDC_6063A.pl/1.2/Wed Nov 24 15:55:51 2004//
;-  ----------------------------------------------------------------------------

;- Hardware register definition

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR System Peripherals
;- *****************************************************************************
;- -------- GPBR : (SYS Offset: 0x1350) GPBR General Purpose Register -------- 
;- -------- GPBR : (SYS Offset: 0x1354) GPBR General Purpose Register -------- 
;- -------- GPBR : (SYS Offset: 0x1358) GPBR General Purpose Register -------- 
;- -------- GPBR : (SYS Offset: 0x135c) GPBR General Purpose Register -------- 

;- *****************************************************************************
;-              SOFTWARE API DEFINITION  FOR SDRAM Controller Interface
;- *****************************************************************************
                ^ 0 ;- AT91S_SDRAMC
SDRAMC_MR       #  4 ;- SDRAM Controller Mode Register
SDRAMC_TR       #  4 ;- SDRAM Controller Refresh Timer Register
SDRAMC_CR       #  4 ;- SDRAM Controller Configuration Register
SDRAMC_HSR      #  4 ;- SDRAM Controller High Speed Register
SDRAMC_LPR      #  4 ;- SDRAM Controller Low Power Register
SDRAMC_IER      #  4 ;- SDRAM Controller Interrupt Enable Register
SDRAMC_IDR      #  4 ;- SDRAM Controller Interrupt Disable Register
SDRAMC_IMR      #  4 ;- SDRAM Controller Interrupt Mask Register
SDRAMC_ISR      #  4 ;- SDRAM Controller Interrupt Mask Register
SDRAMC_MDR      #  4 ;- SDRAM Memory Device Register
;- -------- SDRAMC_MR : (SDRAMC Offset: 0x0) SDRAM Controller Mode Register -------- 
AT91C_SDRAMC_MODE         EQU (0xF:SHL:0) ;- (SDRAMC) Mode
AT91C_SDRAMC_MODE_NORMAL_CMD EQU (0x0) ;- (SDRAMC) Normal Mode
AT91C_SDRAMC_MODE_NOP_CMD EQU (0x1) ;- (SDRAMC) Issue a NOP Command at every access
AT91C_SDRAMC_MODE_PRCGALL_CMD EQU (0x2) ;- (SDRAMC) Issue a All Banks Precharge Command at every access
AT91C_SDRAMC_MODE_LMR_CMD EQU (0x3) ;- (SDRAMC) Issue a Load Mode Register at every access
AT91C_SDRAMC_MODE_RFSH_CMD EQU (0x4) ;- (SDRAMC) Issue a Refresh
AT91C_SDRAMC_MODE_EXT_LMR_CMD EQU (0x5) ;- (SDRAMC) Issue an Extended Load Mode Register
AT91C_SDRAMC_MODE_DEEP_CMD EQU (0x6) ;- (SDRAMC) Enter Deep Power Mode
;- -------- SDRAMC_TR : (SDRAMC Offset: 0x4) SDRAMC Refresh Timer Register -------- 
AT91C_SDRAMC_COUNT        EQU (0xFFF:SHL:0) ;- (SDRAMC) Refresh Counter
;- -------- SDRAMC_CR : (SDRAMC Offset: 0x8) SDRAM Configuration Register -------- 
AT91C_SDRAMC_NC           EQU (0x3:SHL:0) ;- (SDRAMC) Number of Column Bits
AT91C_SDRAMC_NC_8         EQU (0x0) ;- (SDRAMC) 8 Bits
AT91C_SDRAMC_NC_9         EQU (0x1) ;- (SDRAMC) 9 Bits
AT91C_SDRAMC_NC_10        EQU (0x2) ;- (SDRAMC) 10 Bits
AT91C_SDRAMC_NC_11        EQU (0x3) ;- (SDRAMC) 11 Bits
AT91C_SDRAMC_NR           EQU (0x3:SHL:2) ;- (SDRAMC) Number of Row Bits
AT91C_SDRAMC_NR_11        EQU (0x0:SHL:2) ;- (SDRAMC) 11 Bits
AT91C_SDRAMC_NR_12        EQU (0x1:SHL:2) ;- (SDRAMC) 12 Bits
AT91C_SDRAMC_NR_13        EQU (0x2:SHL:2) ;- (SDRAMC) 13 Bits
AT91C_SDRAMC_NB           EQU (0x1:SHL:4) ;- (SDRAMC) Number of Banks
AT91C_SDRAMC_NB_2_BANKS   EQU (0x0:SHL:4) ;- (SDRAMC) 2 banks
AT91C_SDRAMC_NB_4_BANKS   EQU (0x1:SHL:4) ;- (SDRAMC) 4 banks
AT91C_SDRAMC_CAS          EQU (0x3:SHL:5) ;- (SDRAMC) CAS Latency
AT91C_SDRAMC_CAS_2        EQU (0x2:SHL:5) ;- (SDRAMC) 2 cycles
AT91C_SDRAMC_CAS_3        EQU (0x3:SHL:5) ;- (SDRAMC) 3 cycles
AT91C_SDRAMC_DBW          EQU (0x1:SHL:7) ;- (SDRAMC) Data Bus Width
AT91C_SDRAMC_DBW_32_BITS  EQU (0x0:SHL:7) ;- (SDRAMC) 32 Bits datas bus
AT91C_SDRAMC_DBW_16_BITS  EQU (0x1:SHL:7) ;- (SDRAMC) 16 Bits datas bus
AT91C_SDRAMC_TWR          EQU (0xF:SHL:8) ;- (SDRAMC) Number of Write Recovery Time Cycles
AT91C_SDRAMC_TWR_0        EQU (0x0:SHL:8) ;- (SDRAMC) Value :  0
AT91C_SDRAMC_TWR_1        EQU (0x1:SHL:8) ;- (SDRAMC) Value :  1
AT91C_SDRAMC_TWR_2        EQU (0x2:SHL:8) ;- (SDRAMC) Value :  2
AT91C_SDRAMC_TWR_3        EQU (0x3:SHL:8) ;- (SDRAMC) Value :  3
AT91C_SDRAMC_TWR_4        EQU (0x4:SHL:8) ;- (SDRAMC) Value :  4
AT91C_SDRAMC_TWR_5        EQU (0x5:SHL:8) ;- (SDRAMC) Value :  5
AT91C_SDRAMC_TWR_6        EQU (0x6:SHL:8) ;- (SDRAMC) Value :  6
AT91C_SDRAMC_TWR_7        EQU (0x7:SHL:8) ;- (SDRAMC) Value :  7
AT91C_SDRAMC_TWR_8        EQU (0x8:SHL:8) ;- (SDRAMC) Value :  8
AT91C_SDRAMC_TWR_9        EQU (0x9:SHL:8) ;- (SDRAMC) Value :  9
AT91C_SDRAMC_TWR_10       EQU (0xA:SHL:8) ;- (SDRAMC) Value : 10
AT91C_SDRAMC_TWR_11       EQU (0xB:SHL:8) ;- (SDRAMC) Value : 11
AT91C_SDRAMC_TWR_12       EQU (0xC:SHL:8) ;- (SDRAMC) Value : 12
AT91C_SDRAMC_TWR_13       EQU (0xD:SHL:8) ;- (SDRAMC) Value : 13
AT91C_SDRAMC_TWR_14       EQU (0xE:SHL:8) ;- (SDRAMC) Value : 14
AT91C_SDRAMC_TWR_15       EQU (0xF:SHL:8) ;- (SDRAMC) Value : 15
AT91C_SDRAMC_TRC          EQU (0xF:SHL:12) ;- (SDRAMC) Number of RAS Cycle Time Cycles
AT91C_SDRAMC_TRC_0        EQU (0x0:SHL:12) ;- (SDRAMC) Value :  0
AT91C_SDRAMC_TRC_1        EQU (0x1:SHL:12) ;- (SDRAMC) Value :  1
AT91C_SDRAMC_TRC_2        EQU (0x2:SHL:12) ;- (SDRAMC) Value :  2
AT91C_SDRAMC_TRC_3        EQU (0x3:SHL:12) ;- (SDRAMC) Value :  3
AT91C_SDRAMC_TRC_4        EQU (0x4:SHL:12) ;- (SDRAMC) Value :  4
AT91C_SDRAMC_TRC_5        EQU (0x5:SHL:12) ;- (SDRAMC) Value :  5
AT91C_SDRAMC_TRC_6        EQU (0x6:SHL:12) ;- (SDRAMC) Value :  6
AT91C_SDRAMC_TRC_7        EQU (0x7:SHL:12) ;- (SDRAMC) Value :  7
AT91C_SDRAMC_TRC_8        EQU (0x8:SHL:12) ;- (SDRAMC) Value :  8
AT91C_SDRAMC_TRC_9        EQU (0x9:SHL:12) ;- (SDRAMC) Value :  9
AT91C_SDRAMC_TRC_10       EQU (0xA:SHL:12) ;- (SDRAMC) Value : 10
AT91C_SDRAMC_TRC_11       EQU (0xB:SHL:12) ;- (SDRAMC) Value : 11
AT91C_SDRAMC_TRC_12       EQU (0xC:SHL:12) ;- (SDRAMC) Value : 12
AT91C_SDRAMC_TRC_13       EQU (0xD:SHL:12) ;- (SDRAMC) Value : 13
AT91C_SDRAMC_TRC_14       EQU (0xE:SHL:12) ;- (SDRAMC) Value : 14
AT91C_SDRAMC_TRC_15       EQU (0xF:SHL:12) ;- (SDRAMC) Value : 15
AT91C_SDRAMC_TRP          EQU (0xF:SHL:16) ;- (SDRAMC) Number of RAS Precharge Time Cycles
AT91C_SDRAMC_TRP_0        EQU (0x0:SHL:16) ;- (SDRAMC) Value :  0
AT91C_SDRAMC_TRP_1        EQU (0x1:SHL:16) ;- (SDRAMC) Value :  1
AT91C_SDRAMC_TRP_2        EQU (0x2:SHL:16) ;- (SDRAMC) Value :  2
AT91C_SDRAMC_TRP_3        EQU (0x3:SHL:16) ;- (SDRAMC) Value :  3
AT91C_SDRAMC_TRP_4        EQU (0x4:SHL:16) ;- (SDRAMC) Value :  4
AT91C_SDRAMC_TRP_5        EQU (0x5:SHL:16) ;- (SDRAMC) Value :  5
AT91C_SDRAMC_TRP_6        EQU (0x6:SHL:16) ;- (SDRAMC) Value :  6
AT91C_SDRAMC_TRP_7        EQU (0x7:SHL:16) ;- (SDRAMC) Value :  7
AT91C_SDRAMC_TRP_8        EQU (0x8:SHL:16) ;- (SDRAMC) Value :  8
AT91C_SDRAMC_TRP_9        EQU (0x9:SHL:16) ;- (SDRAMC) Value :  9
AT91C_SDRAMC_TRP_10       EQU (0xA:SHL:16) ;- (SDRAMC) Value : 10
AT91C_SDRAMC_TRP_11       EQU (0xB:SHL:16) ;- (SDRAMC) Value : 11
AT91C_SDRAMC_TRP_12       EQU (0xC:SHL:16) ;- (SDRAMC) Value : 12
AT91C_SDRAMC_TRP_13       EQU (0xD:SHL:16) ;- (SDRAMC) Value : 13
AT91C_SDRAMC_TRP_14       EQU (0xE:SHL:16) ;- (SDRAMC) Value : 14
AT91C_SDRAMC_TRP_15       EQU (0xF:SHL:16) ;- (SDRAMC) Value : 15
AT91C_SDRAMC_TRCD         EQU (0xF:SHL:20) ;- (SDRAMC) Number of RAS to CAS Delay Cycles
AT91C_SDRAMC_TRCD_0       EQU (0x0:SHL:20) ;- (SDRAMC) Value :  0
AT91C_SDRAMC_TRCD_1       EQU (0x1:SHL:20) ;- (SDRAMC) Value :  1
AT91C_SDRAMC_TRCD_2       EQU (0x2:SHL:20) ;- (SDRAMC) Value :  2
AT91C_SDRAMC_TRCD_3       EQU (0x3:SHL:20) ;- (SDRAMC) Value :  3
AT91C_SDRAMC_TRCD_4       EQU (0x4:SHL:20) ;- (SDRAMC) Value :  4
AT91C_SDRAMC_TRCD_5       EQU (0x5:SHL:20) ;- (SDRAMC) Value :  5
AT91C_SDRAMC_TRCD_6       EQU (0x6:SHL:20) ;- (SDRAMC) Value :  6
AT91C_SDRAMC_TRCD_7       EQU (0x7:SHL:20) ;- (SDRAMC) Value :  7
AT91C_SDRAMC_TRCD_8       EQU (0x8:SHL:20) ;- (SDRAMC) Value :  8
AT91C_SDRAMC_TRCD_9       EQU (0x9:SHL:20) ;- (SDRAMC) Value :  9
AT91C_SDRAMC_TRCD_10      EQU (0xA:SHL:20) ;- (SDRAMC) Value : 10
AT91C_SDRAMC_TRCD_11      EQU (0xB:SHL:20) ;- (SDRAMC) Value : 11
AT91C_SDRAMC_TRCD_12      EQU (0xC:SHL:20) ;- (SDRAMC) Value : 12
AT91C_SDRAMC_TRCD_13      EQU (0xD:SHL:20) ;- (SDRAMC) Value : 13
AT91C_SDRAMC_TRCD_14      EQU (0xE:SHL:20) ;- (SDRAMC) Value : 14
AT91C_SDRAMC_TRCD_15      EQU (0xF:SHL:20) ;- (SDRAMC) Value : 15
AT91C_SDRAMC_TRAS         EQU (0xF:SHL:24) ;- (SDRAMC) Number of RAS Active Time Cycles
AT91C_SDRAMC_TRAS_0       EQU (0x0:SHL:24) ;- (SDRAMC) Value :  0
AT91C_SDRAMC_TRAS_1       EQU (0x1:SHL:24) ;- (SDRAMC) Value :  1
AT91C_SDRAMC_TRAS_2       EQU (0x2:SHL:24) ;- (SDRAMC) Value :  2
AT91C_SDRAMC_TRAS_3       EQU (0x3:SHL:24) ;- (SDRAMC) Value :  3
AT91C_SDRAMC_TRAS_4       EQU (0x4:SHL:24) ;- (SDRAMC) Value :  4
AT91C_SDRAMC_TRAS_5       EQU (0x5:SHL:24) ;- (SDRAMC) Value :  5
AT91C_SDRAMC_TRAS_6       EQU (0x6:SHL:24) ;- (SDRAMC) Value :  6
AT91C_SDRAMC_TRAS_7       EQU (0x7:SHL:24) ;- (SDRAMC) Value :  7
AT91C_SDRAMC_TRAS_8       EQU (0x8:SHL:24) ;- (SDRAMC) Value :  8
AT91C_SDRAMC_TRAS_9       EQU (0x9:SHL:24) ;- (SDRAMC) Value :  9
AT91C_SDRAMC_TRAS_10      EQU (0xA:SHL:24) ;- (SDRAMC) Value : 10
AT91C_SDRAMC_TRAS_11      EQU (0xB:SHL:24) ;- (SDRAMC) Value : 11
AT91C_SDRAMC_TRAS_12      EQU (0xC:SHL:24) ;- (SDRAMC) Value : 12
AT91C_SDRAMC_TRAS_13      EQU (0xD:SHL:24) ;- (SDRAMC) Value : 13
AT91C_SDRAMC_TRAS_14      EQU (0xE:SHL:24) ;- (SDRAMC) Value : 14
AT91C_SDRAMC_TRAS_15      EQU (0xF:SHL:24) ;- (SDRAMC) Value : 15
AT91C_SDRAMC_TXSR         EQU (0xF:SHL:28) ;- (SDRAMC) Number of Command Recovery Time Cycles
AT91C_SDRAMC_TXSR_0       EQU (0x0:SHL:28) ;- (SDRAMC) Value :  0