📄 dianti.rpt
字号:
- 7 - C 03 AND2 s 0 3 0 2 ~2354~1
- 2 - C 17 AND2 0 4 0 2 :2506
- 4 - C 17 OR2 0 4 0 1 :2629
- 3 - C 17 OR2 0 4 0 1 :2630
- 3 - C 11 AND2 s 0 3 0 2 ~2675~1
- 7 - C 11 AND2 s 1 3 0 1 ~2675~2
- 4 - C 18 AND2 s 0 3 0 2 ~2763~1
- 1 - C 05 AND2 s 1 2 0 1 ~2763~2
- 1 - C 18 AND2 0 3 0 2 :2915
- 5 - C 18 OR2 0 4 0 1 :3038
- 3 - C 18 OR2 0 4 0 1 :3039
- 3 - C 08 AND2 s 1 3 0 1 ~3077~1
- 6 - C 18 OR2 0 4 0 1 :3163
- 4 - D 10 AND2 s ! 1 1 0 4 ~3267~1
- 1 - F 03 AND2 s 3 0 0 3 ~3617~1
- 7 - C 18 OR2 1 3 0 1 :3771
- 2 - C 18 OR2 1 3 0 1 :3774
- 5 - C 17 OR2 1 3 0 1 :3777
- 1 - C 17 OR2 1 3 0 1 :3780
- 7 - A 11 OR2 1 3 0 1 :3787
- 5 - A 11 OR2 2 2 0 1 :3788
- 5 - C 08 OR2 s 0 2 0 1 ~4532~1
- 3 - C 06 OR2 s 0 2 0 1 ~4533~1
- 2 - C 09 OR2 s 0 2 0 1 ~4534~1
- 4 - C 07 OR2 s 0 2 0 1 ~4535~1
- 3 - A 30 OR2 s 0 2 0 1 ~4536~1
- 1 - A 02 OR2 s 0 2 0 1 ~4537~1
- 4 - A 15 OR2 s 0 2 0 15 ~4885~1
- 3 - C 15 OR2 s 2 0 0 25 ~4897~1
- 2 - A 21 AND2 s 0 2 0 3 ~4897~2
- 6 - A 36 AND2 s 0 3 0 1 ~4897~3
- 6 - A 24 AND2 s 1 3 0 1 ~4897~4
- 4 - A 21 OR2 s 1 3 0 1 ~4909~1
- 5 - A 31 OR2 s 0 2 0 2 ~4933~1
- 4 - C 11 OR2 s 1 2 0 1 ~4969~1
- 7 - C 02 OR2 s 2 2 0 1 ~4981~1
- 8 - C 03 OR2 s 1 3 0 1 ~4993~1
- 1 - C 11 OR2 s 1 2 0 1 ~5005~1
- 4 - C 02 OR2 s 2 1 0 1 ~5017~1
- 6 - C 03 OR2 s 1 2 0 1 ~5029~1
- 1 - C 14 OR2 s 3 1 0 2 ~5041~1
- 2 - A 16 OR2 s 3 1 0 1 ~5053~1
- 2 - C 05 OR2 s 0 4 0 1 ~5089~1
- 1 - C 16 OR2 s 1 3 0 1 ~5089~2
- 1 - A 05 OR2 s 1 3 0 1 ~5089~3
- 5 - C 10 OR2 s 2 2 0 1 ~5089~4
- 3 - A 05 OR2 s 1 3 0 1 ~5089~5
- 6 - A 05 OR2 s 1 3 0 1 ~5089~6
- 7 - A 05 OR2 s 1 3 0 1 ~5089~7
- 8 - C 10 OR2 s 3 1 0 4 ~5089~8
- 6 - C 02 OR2 s 1 1 0 4 ~5089~9
- 6 - A 16 OR2 s 2 1 0 3 ~5101~1
- 5 - D 17 OR2 s 1 3 0 1 ~5137~1
- 2 - D 17 OR2 s 4 0 0 2 ~5161~1
- 2 - C 10 OR2 s 2 2 0 1 ~5173~1
- 3 - C 10 OR2 s 4 0 0 1 ~5173~2
- 4 - F 03 OR2 s 3 0 0 1 ~5185~1
- 8 - C 02 OR2 s 1 1 0 3 ~5209~1
- 7 - C 10 OR2 s 1 1 0 2 ~5209~2
- 4 - C 16 OR2 s 0 4 0 1 ~5209~3
- 5 - C 16 AND2 s 2 2 0 1 ~5209~4
- 6 - C 16 OR2 s 1 2 0 1 ~5209~5
- 7 - C 16 OR2 s 0 4 0 1 ~5209~6
- 8 - C 16 OR2 s 0 4 0 1 ~5209~7
- 3 - C 16 OR2 s 1 3 0 1 ~5209~8
- 8 - A 05 OR2 s 0 4 0 1 ~5209~9
- 2 - A 05 OR2 s 1 3 0 1 ~5209~10
- 5 - A 02 OR2 s 1 3 0 1 ~5209~11
- 6 - A 02 OR2 s 1 3 0 1 ~5221~1
- 3 - A 15 OR2 s 1 3 0 1 ~5233~1
- 8 - A 11 OR2 0 4 0 1 :5239
- 4 - A 27 OR2 s 1 2 0 1 ~5269~1
- 6 - A 27 OR2 s 1 3 0 1 ~5269~2
- 7 - A 27 OR2 s 1 3 0 1 ~5269~3
- 2 - A 24 OR2 s 0 2 0 1 ~5281~1
- 3 - A 24 OR2 s 2 2 0 1 ~5281~2
- 5 - A 24 OR2 s 0 4 0 1 ~5281~3
- 7 - A 24 OR2 s 0 4 0 1 ~5281~4
- 8 - A 24 OR2 s 0 4 0 1 ~5281~5
- 2 - A 15 AND2 s 0 2 0 21 ~5307~1
- 1 - A 27 OR2 s 1 2 0 1 ~5319~1
- 7 - A 36 OR2 s 0 4 0 1 ~5319~2
- 8 - A 36 OR2 s 0 3 0 1 ~5319~3
- 3 - E 34 AND2 s ! 1 1 0 7 ~5331~1
- 7 - E 36 OR2 s 0 4 0 1 ~5331~2
- 5 - E 34 AND2 s ! 0 2 0 2 ~5343~1
- 7 - E 34 OR2 s 0 4 0 1 ~5343~2
- 8 - E 34 OR2 s 0 4 0 1 ~5343~3
- 2 - A 32 AND2 s ! 1 1 0 5 ~5355~1
- 4 - E 34 OR2 s 0 3 0 2 ~5355~2
- 4 - E 36 OR2 s 0 3 0 1 ~5355~3
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
p = Packed register
Device-Specific Information: f:\dianti\dianti.rpt
dianti
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 45/144( 31%) 10/ 72( 13%) 6/ 72( 8%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 1/144( 0%) 1/ 72( 1%) 0/ 72( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
C: 50/144( 34%) 18/ 72( 25%) 0/ 72( 0%) 5/16( 31%) 4/16( 25%) 0/16( 0%)
D: 3/144( 2%) 6/ 72( 8%) 0/ 72( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
E: 9/144( 6%) 2/ 72( 2%) 3/ 72( 4%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
F: 2/144( 1%) 6/ 72( 8%) 0/ 72( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
02: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 2/24( 8%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
06: 3/24( 12%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
07: 5/24( 20%) 1/4( 25%) 1/4( 25%) 0/4( 0%)
08: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
09: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
10: 4/24( 16%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 3/24( 12%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
15: 5/24( 20%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
18: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
25: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
26: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
27: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
28: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
29: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
30: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
31: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
32: 3/24( 12%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
33: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
34: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
35: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
36: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\dianti\dianti.rpt
dianti
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 83 clk
Device-Specific Information: f:\dianti\dianti.rpt
dianti
** EQUATIONS **
c_d2 : INPUT;
c_d3 : INPUT;
c_d4 : INPUT;
c_d5 : INPUT;
c_d6 : INPUT;
clk : INPUT;
clr : INPUT;
c_u1 : INPUT;
c_u2 : INPUT;
c_u3 : INPUT;
c_u4 : INPUT;
c_u5 : INPUT;
deng : INPUT;
d1 : INPUT;
d2 : INPUT;
d3 : INPUT;
d4 : INPUT;
d5 : INPUT;
d6 : INPUT;
full : INPUT;
g1 : INPUT;
g2 : INPUT;
g3 : INPUT;
g4 : INPUT;
g5 : INPUT;
g6 : INPUT;
quick : INPUT;
-- Node name is 'alarm'
-- Equation name is 'alarm', type is output
alarm = _LC7_C15;
-- Node name is ':142' = 'cc_d0'
-- Equation name is 'cc_d0', location is LC3_A27, type is buried.
cc_d0 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = cc_d0 & clr
# cc_d0 & full
# cc_d0 & q;
-- Node name is ':141' = 'cc_d1'
-- Equation name is 'cc_d1', location is LC7_A30, type is buried.
cc_d1 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = c_d22 & !_LC3_C15 & !q
# cc_d1 & q
# cc_d1 & _LC3_C15;
-- Node name is ':140' = 'cc_d2'
-- Equation name is 'cc_d2', location is LC7_C7, type is buried.
cc_d2 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = c_d33 & !_LC3_C15 & !q
# cc_d2 & q
# cc_d2 & _LC3_C15;
-- Node name is ':139' = 'cc_d3'
-- Equation name is 'cc_d3', location is LC4_C9, type is buried.
cc_d3 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = c_d44 & !_LC3_C15 & !q
# cc_d3 & q
# cc_d3 & _LC3_C15;
-- Node name is ':138' = 'cc_d4'
-- Equation name is 'cc_d4', location is LC6_C6, type is buried.
cc_d4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = c_d55 & !_LC3_C15 & !q
# cc_d4 & q
# cc_d4 & _LC3_C15;
-- Node name is ':137' = 'cc_d5'
-- Equation name is 'cc_d5', location is LC8_C8, type is buried.
cc_d5 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = c_d66 & !_LC3_C15 & !q
# cc_d5 & q
# cc_d5 & _LC3_C15;
-- Node name is ':136' = 'cc_u0'
-- Equation name is 'cc_u0', location is LC1_A15, type is buried.
cc_u0 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = c_u11 & !_LC3_C15 & !q
# cc_u0 & q
# cc_u0 & _LC3_C15;
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