📄 dianti.rpt
字号:
D: 0 0 0 0 0 0 0 0 0 2 0 0 0 0 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 10/0
E: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8 0 8 16/0
F: 0 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 8/0
Total: 0 16 16 0 10 10 8 8 8 10 16 0 0 8 12 16 16 7 0 0 0 3 0 0 8 0 8 8 0 0 8 8 1 0 8 0 16 229/0
Device-Specific Information: f:\dianti\dianti.rpt
dianti
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
67 - - - 08 INPUT ^ 0 0 0 3 c_d2
68 - - - 07 INPUT ^ 0 0 0 2 c_d3
110 - - - 02 INPUT ^ 0 0 0 3 c_d4
112 - - - 04 INPUT ^ 0 0 0 2 c_d5
14 - - C -- INPUT ^ 0 0 0 1 c_d6
55 - - - -- INPUT G ^ 0 0 0 0 clk
141 - - - 33 INPUT ^ 0 0 0 11 clr
69 - - - 06 INPUT ^ 0 0 0 4 c_u1
17 - - C -- INPUT ^ 0 0 0 3 c_u2
12 - - C -- INPUT ^ 0 0 0 2 c_u3
120 - - - 14 INPUT ^ 0 0 0 2 c_u4
73 - - - 01 INPUT ^ 0 0 0 1 c_u5
48 - - - 24 INPUT ^ 0 0 0 3 deng
122 - - - 18 INPUT ^ 0 0 0 4 d1
72 - - - 03 INPUT ^ 0 0 0 3 d2
65 - - - 09 INPUT ^ 0 0 0 2 d3
13 - - C -- INPUT ^ 0 0 0 3 d4
11 - - C -- INPUT ^ 0 0 0 2 d5
121 - - - 17 INPUT ^ 0 0 0 1 d6
37 - - - 35 INPUT ^ 0 0 0 9 full
124 - - - -- INPUT ^ 0 0 0 18 g1
125 - - - -- INPUT ^ 0 0 0 16 g2
56 - - - -- INPUT ^ 0 0 0 16 g3
126 - - - -- INPUT ^ 0 0 0 14 g4
54 - - - -- INPUT ^ 0 0 0 13 g5
111 - - - 03 INPUT ^ 0 0 0 7 g6
41 - - - 31 INPUT ^ 0 0 0 10 quick
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\dianti\dianti.rpt
dianti
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
18 - - C -- OUTPUT 0 1 0 0 alarm
131 - - - 23 OUTPUT 0 1 0 0 door0
7 - - A -- OUTPUT 0 1 0 0 door1
140 - - - 32 OUTPUT 0 1 0 0 down
133 - - - 28 OUTPUT 0 1 0 0 led_c_d0
136 - - - 30 OUTPUT 0 1 0 0 led_c_d1
99 - - B -- OUTPUT 0 1 0 0 led_c_d2
87 - - E -- OUTPUT 0 1 0 0 led_c_d3
114 - - - 06 OUTPUT 0 1 0 0 led_c_d4
96 - - C -- OUTPUT 0 1 0 0 led_c_d5
101 - - A -- OUTPUT 0 1 0 0 led_c_u0
44 - - - 29 OUTPUT 0 1 0 0 led_c_u1
116 - - - 07 OUTPUT 0 1 0 0 led_c_u2
64 - - - 10 OUTPUT 0 1 0 0 led_c_u3
113 - - - 05 OUTPUT 0 1 0 0 led_c_u4
80 - - F -- OUTPUT 0 1 0 0 led_c_u5
100 - - A -- OUTPUT 0 1 0 0 led_d0
135 - - - 29 OUTPUT 0 1 0 0 led_d1
10 - - B -- OUTPUT 0 1 0 0 led_d2
95 - - C -- OUTPUT 0 1 0 0 led_d3
70 - - - 05 OUTPUT 0 1 0 0 led_d4
97 - - C -- OUTPUT 0 1 0 0 led_d5
78 - - F -- OUTPUT 0 1 0 0 led0
79 - - F -- OUTPUT 0 1 0 0 led1
86 - - E -- OUTPUT 0 1 0 0 led2
89 - - D -- OUTPUT 0 1 0 0 led3
81 - - F -- OUTPUT 0 1 0 0 led4
88 - - D -- OUTPUT 0 1 0 0 led5
92 - - D -- OUTPUT 0 1 0 0 led6
27 - - E -- OUTPUT 0 1 0 0 long
91 - - D -- OUTPUT 0 1 0 0 ud
8 - - A -- OUTPUT 0 1 0 0 up
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\dianti\dianti.rpt
dianti
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 5 - C 14 AND2 s 1 1 0 1 c_d2~1
- 7 - C 14 AND2 s 2 1 0 1 c_d2~2
- 8 - C 14 AND2 s 2 1 0 3 c_d2~3
- 6 - C 11 AND2 s 1 1 0 1 c_d2~4
- 5 - C 11 AND2 s 3 1 0 1 c_d2~5
- 4 - A 31 AND2 s 1 3 0 2 clr~1
- 6 - A 21 AND2 s 1 3 0 1 clr~2
- 3 - F 03 AND2 s 2 1 0 1 clr~3
- 3 - D 17 AND2 s 4 0 0 2 clr~4
- 5 - F 03 AND2 s 2 2 0 1 clr~5
- 7 - F 03 AND2 s 2 2 0 1 clr~6
- 4 - D 17 AND2 s 3 0 0 1 clr~7
- 7 - D 17 OR2 s 2 1 0 1 clr~8
- 1 - C 03 AND2 s 2 1 0 1 c_u1~1
- 4 - C 03 AND2 s 3 1 0 1 c_u1~2
- 5 - C 03 AND2 s 3 1 0 2 c_u1~3
- 1 - A 16 AND2 s 1 1 0 1 d1~1
- 8 - A 16 AND2 s 2 1 0 1 d1~2
- 1 - C 02 AND2 s 3 1 0 3 d1~3
- 5 - C 02 AND2 s 3 1 0 1 d1~4
- 6 - E 36 OR2 ! 0 2 0 1 |LPM_ADD_SUB:586|addcore:adder|:55
- 5 - A 27 DFFE + 1 2 1 0 :28
- 1 - A 24 DFFE + 2 1 1 1 :30
- 1 - D 17 DFFE + 0 3 1 0 :32
- 8 - D 17 DFFE + 0 3 1 0 :34
- 2 - F 03 DFFE + 0 3 1 0 :36
- 6 - D 17 DFFE + 0 3 1 0 :38
- 4 - C 10 DFFE + 1 3 1 1 :40
- 6 - F 03 DFFE + 0 3 1 0 :42
- 8 - F 03 DFFE + 1 2 1 0 :44
- 4 - C 15 DFFE + 0 1 1 0 :46
- 2 - C 06 DFFE + 0 1 1 0 :48
- 6 - C 09 DFFE + 0 1 1 0 :50
- 2 - C 07 DFFE + 0 1 1 0 :52
- 4 - A 30 DFFE + 0 1 1 0 :54
- 6 - A 15 DFFE + 0 1 1 0 :56
- 4 - C 08 DFFE + 0 1 1 0 :58
- 8 - C 06 DFFE + 0 1 1 0 :60
- 1 - C 09 DFFE + 0 1 1 0 :62
- 3 - C 07 DFFE + 0 1 1 0 :64
- 1 - A 30 DFFE + 0 1 1 0 :66
- 8 - A 27 DFFE + 0 1 1 0 :68
- 1 - C 08 DFFE + 0 1 1 0 :70
- 1 - C 06 DFFE + 0 1 1 0 :72
- 8 - C 09 DFFE + 0 1 1 0 :74
- 6 - C 07 DFFE + 0 1 1 0 :76
- 6 - A 30 DFFE + 0 1 1 0 :78
- 8 - A 02 DFFE + 0 1 1 0 :80
- 2 - E 34 DFFE + 1 2 1 0 :82
- 2 - D 10 DFFE + 0 1 1 0 :84
- 7 - C 15 DFFE + 2 0 1 0 :86
- 7 - A 31 DFFE + 0 3 1 0 :88
- 3 - A 31 DFFE + 0 3 1 0 :90
- 3 - A 26 DFFE + 0 3 0 6 q12 (:92)
- 5 - A 36 DFFE + 0 3 0 6 q11 (:93)
- 1 - A 36 DFFE + 0 4 0 9 q10 (:94)
- 8 - E 36 DFFE + 1 2 0 1 q22 (:95)
- 6 - E 34 DFFE + 1 3 0 4 q21 (:96)
- 2 - E 36 DFFE + 1 2 0 4 q20 (:97)
- 7 - A 15 DFFE + 0 1 0 32 q (:98)
- 1 - A 11 DFFE + 2 1 0 13 opendoor (:99)
- 3 - E 36 AND2 s 0 3 0 1 en_up~1 (~100~1)
- 5 - E 36 AND2 s 0 4 0 1 en_up~2 (~100~2)
- 4 - A 02 DFFE + 0 3 0 9 en_up (:100)
- 1 - A 31 DFFE + 0 3 0 28 updown (:101)
- 5 - A 05 DFFE + 0 3 0 7 en_dw (:102)
- 2 - A 02 DFFE + 1 2 0 4 d11 (:103)
- 5 - A 15 DFFE + 1 2 0 4 c_u11 (:104)
- 5 - C 15 DFFE + 0 3 0 9 dd_cc5 (:105)
- 5 - C 06 DFFE + 0 3 0 7 dd_cc4 (:106)
- 5 - C 09 DFFE + 0 3 0 2 dd_cc3 (:107)
- 1 - C 07 DFFE + 0 3 0 4 dd_cc2 (:108)
- 2 - A 30 DFFE + 0 3 0 3 dd_cc1 (:109)
- 2 - A 11 DFFE + 0 3 0 1 dd_cc0 (:110)
- 5 - A 16 DFFE + 1 2 0 4 d22 (:111)
- 7 - A 16 DFFE + 0 3 0 2 c_u22 (:112)
- 2 - A 31 DFFE + 0 3 0 3 c_d22 (:113)
- 3 - A 16 DFFE + 1 2 0 5 d33 (:114)
- 6 - C 14 DFFE + 0 3 0 3 c_u33 (:115)
- 3 - C 14 DFFE + 0 3 0 3 c_d33 (:116)
- 3 - C 02 DFFE + 1 2 0 5 d44 (:117)
- 3 - C 03 DFFE + 1 2 0 3 c_u44 (:118)
- 8 - C 11 DFFE + 1 2 0 3 c_d44 (:119)
- 2 - C 02 DFFE + 2 2 0 6 d55 (:120)
- 2 - C 03 DFFE + 2 2 0 4 c_u55 (:121)
- 2 - C 11 DFFE + 1 2 0 3 c_d55 (:122)
- 7 - C 08 DFFE + 0 3 0 3 d66 (:123)
- 2 - C 08 DFFE + 0 3 0 3 c_d66 (:124)
- 6 - C 08 DFFE + 0 3 0 2 dd5 (:125)
- 4 - C 06 DFFE + 0 3 0 2 dd4 (:126)
- 3 - C 09 DFFE + 0 3 0 2 dd3 (:127)
- 5 - C 07 DFFE + 0 3 0 2 dd2 (:128)
- 5 - A 30 DFFE + 0 3 0 2 dd1 (:129)
- 7 - A 02 DFFE + 0 3 0 2 dd0 (:130)
- 1 - C 15 DFFE + 2 1 0 2 cc_u5 (:131)
- 7 - C 06 DFFE + 0 3 0 2 cc_u4 (:132)
- 7 - C 09 DFFE + 0 3 0 2 cc_u3 (:133)
- 8 - C 07 DFFE + 0 3 0 2 cc_u2 (:134)
- 8 - A 30 DFFE + 0 3 0 2 cc_u1 (:135)
- 1 - A 15 DFFE + 0 3 0 2 cc_u0 (:136)
- 8 - C 08 DFFE + 0 3 0 2 cc_d5 (:137)
- 6 - C 06 DFFE + 0 3 0 2 cc_d4 (:138)
- 4 - C 09 DFFE + 0 3 0 2 cc_d3 (:139)
- 7 - C 07 DFFE + 0 3 0 2 cc_d2 (:140)
- 7 - A 30 DFFE + 0 3 0 2 cc_d1 (:141)
- 3 - A 27 DFFE + 2 1 0 2 cc_d0 (:142)
- 1 - E 36 AND2 0 3 0 13 :462
- 1 - A 26 AND2 0 3 0 5 :548
- 2 - A 26 OR2 ! 0 3 0 3 :557
- 4 - A 26 OR2 0 4 0 1 :748
- 2 - A 27 OR2 s ! 1 1 0 4 ~935~1
- 4 - A 24 AND2 s 1 1 0 5 ~991~1
- 6 - A 26 OR2 0 3 0 1 :1002
- 7 - A 26 OR2 1 3 0 1 :1008
- 5 - A 26 OR2 1 3 0 1 :1012
- 2 - A 36 OR2 0 4 0 1 :1029
- 3 - A 36 OR2 0 4 0 1 :1033
- 1 - E 34 AND2 s 0 2 0 9 ~1198~1
- 8 - A 26 OR2 0 4 0 1 :1204
- 4 - A 36 OR2 0 4 0 1 :1210
- 3 - A 02 AND2 s 1 3 0 1 ~1287~1
- 6 - A 11 AND2 0 4 0 1 :1405
- 8 - A 31 AND2 s 0 3 0 2 ~1448~1
- 6 - A 31 OR2 0 2 0 1 :1448
- 5 - A 06 AND2 0 2 0 3 :1457
- 4 - A 05 AND2 s 0 2 0 1 ~1536~1
- 4 - A 16 AND2 ! 0 2 0 3 :1536
- 1 - A 06 AND2 ! 0 2 0 5 :1543
- 3 - A 11 AND2 0 4 0 1 :1688
- 4 - A 11 OR2 0 4 0 1 :1810
- 2 - C 14 AND2 s 0 3 0 2 ~1857~1
- 4 - C 14 AND2 s 0 3 0 2 ~1945~1
- 1 - C 10 AND2 s 1 2 0 1 ~1945~2
- 2 - C 16 AND2 ! 0 3 0 7 :1952
- 6 - C 17 AND2 0 3 0 2 :2097
- 8 - C 17 OR2 0 4 0 1 :2220
- 7 - C 17 OR2 0 4 0 1 :2221
- 6 - C 10 AND2 s 0 3 0 2 ~2266~1
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