📄 system.rpt
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Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 229
Total flipflops required: 83
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 109/1728 ( 6%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 EA 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Total(LC/EC)
A: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 8 0 0 8 0 8 0 8 0 0 0 8 0 8 8 58/0
B: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
C: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 4/0
D: 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0/0
E: 8 0 0 8 8 8 0 8 0 8 0 0 0 0 8 8 8 0 0 0 0 0 8 5 8 0 7 0 0 8 2 8 8 8 8 8 0 150/0
F: 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 8 0 0 0 0 0 8 0 0 0 0 0 17/0
Total: 8 0 0 8 8 8 0 8 0 8 0 0 1 0 8 8 8 0 0 1 4 1 16 5 8 16 7 8 0 16 2 16 8 16 8 16 8 229/0
Device-Specific Information: f:\dianti\system.rpt
system
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
39 - - - 33 INPUT ^ 0 0 0 3 C_D2
46 - - - 27 INPUT ^ 0 0 0 2 C_D3
114 - - - 06 INPUT ^ 0 0 0 3 C_D4
109 - - - 01 INPUT ^ 0 0 0 2 C_D5
72 - - - 03 INPUT ^ 0 0 0 1 C_D6
55 - - - -- INPUT G ^ 0 0 0 0 CLK
44 - - - 29 INPUT ^ 0 0 0 11 CLR
42 - - - 28 INPUT ^ 0 0 0 4 C_U1
136 - - - 30 INPUT ^ 0 0 0 3 C_U2
131 - - - 23 INPUT ^ 0 0 0 2 C_U3
110 - - - 02 INPUT ^ 0 0 0 2 C_U4
69 - - - 06 INPUT ^ 0 0 0 1 C_U5
100 - - A -- INPUT ^ 0 0 0 3 DENG
83 - - E -- INPUT ^ 0 0 0 4 D1
86 - - E -- INPUT ^ 0 0 0 3 D2
27 - - E -- INPUT ^ 0 0 0 2 D3
117 - - - 08 INPUT ^ 0 0 0 3 D4
62 - - - 12 INPUT ^ 0 0 0 2 D5
122 - - - 18 INPUT ^ 0 0 0 1 D6
140 - - - 32 INPUT ^ 0 0 0 8 FULL
126 - - - -- INPUT ^ 0 0 0 16 G1
41 - - - 31 INPUT ^ 0 0 0 11 G2
124 - - - -- INPUT ^ 0 0 0 15 G3
56 - - - -- INPUT ^ 0 0 0 14 G4
54 - - - -- INPUT ^ 0 0 0 13 G5
125 - - - -- INPUT ^ 0 0 0 7 G6
101 - - A -- INPUT ^ 0 0 0 10 QUICK
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information: f:\dianti\system.rpt
system
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
28 - - E -- OUTPUT 0 1 0 0 ALARM
132 - - - 26 OUTPUT 0 1 0 0 DOOR0
102 - - A -- OUTPUT 0 1 0 0 DOOR1
7 - - A -- OUTPUT 0 1 0 0 DOWN
26 - - E -- OUTPUT 0 1 0 0 LED_C_D0
22 - - D -- OUTPUT 0 1 0 0 LED_C_D1
144 - - - 36 OUTPUT 0 1 0 0 LED_C_D2
88 - - D -- OUTPUT 0 1 0 0 LED_C_D3
14 - - C -- OUTPUT 0 1 0 0 LED_C_D4
59 - - - 16 OUTPUT 0 1 0 0 LED_C_D5
48 - - - 24 OUTPUT 0 1 0 0 LED_C_U0
29 - - E -- OUTPUT 0 1 0 0 LED_C_U1
143 - - - 35 OUTPUT 0 1 0 0 LED_C_U2
67 - - - 08 OUTPUT 0 1 0 0 LED_C_U3
87 - - E -- OUTPUT 0 1 0 0 LED_C_U4
90 - - D -- OUTPUT 0 1 0 0 LED_C_U5
142 - - - 34 OUTPUT 0 1 0 0 LED_D0
138 - - - 31 OUTPUT 0 1 0 0 LED_D1
37 - - - 35 OUTPUT 0 1 0 0 LED_D2
68 - - - 07 OUTPUT 0 1 0 0 LED_D3
96 - - C -- OUTPUT 0 1 0 0 LED_D4
60 - - - 15 OUTPUT 0 1 0 0 LED_D5
32 - - F -- OUTPUT 0 1 0 0 LED0
78 - - F -- OUTPUT 0 1 0 0 LED1
33 - - F -- OUTPUT 0 1 0 0 LED2
31 - - F -- OUTPUT 0 1 0 0 LED3
30 - - F -- OUTPUT 0 1 0 0 LED4
13 - - C -- OUTPUT 0 1 0 0 LED5
80 - - F -- OUTPUT 0 1 0 0 LED6
8 - - A -- OUTPUT 0 1 0 0 LONG
82 - - F -- OUTPUT 0 1 0 0 UD
133 - - - 28 OUTPUT 0 1 0 0 UP
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
^ = Increased input delay
* = PCI I/O is enabled
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\dianti\system.rpt
system
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 4 - E 29 AND2 s 1 1 0 1 C_D2~1
- 2 - E 29 AND2 s 2 1 0 3 C_D2~2
- 6 - E 10 AND2 s 1 1 0 1 C_D2~3
- 8 - E 10 AND2 s 3 1 0 1 C_D2~4
- 2 - A 19 AND2 s 1 1 0 7 CLR~1
- 6 - A 27 AND2 s 1 3 0 2 CLR~2
- 1 - F 31 AND2 s 0 2 0 1 CLR~3
- 6 - F 25 AND2 s 2 2 0 1 CLR~4
- 8 - F 25 AND2 s 2 2 0 1 CLR~5
- 1 - C 20 AND2 s 3 0 0 1 CLR~6
- 4 - C 20 OR2 s 2 1 0 1 CLR~7
- 7 - A 35 AND2 s 1 3 0 1 CLR~8
- 5 - E 33 AND2 s 2 1 0 1 C_U1~1
- 6 - E 22 AND2 s 2 1 0 1 C_U1~2
- 7 - E 22 AND2 s 3 1 0 2 C_U1~3
- 1 - A 33 AND2 s 0 3 0 1 DENG~1
- 5 - A 33 OR2 ! 0 2 0 1 |DIANTI:28|LPM_ADD_SUB:586|addcore:adder|:55
- 1 - A 22 DFFE + 1 2 1 0 |DIANTI:28|:28
- 2 - A 25 DFFE + 1 2 1 1 |DIANTI:28|:30
- 4 - F 31 DFFE + 0 2 1 0 |DIANTI:28|:32
- 2 - C 20 DFFE + 0 3 1 0 |DIANTI:28|:34
- 1 - F 25 DFFE + 0 3 1 0 |DIANTI:28|:36
- 3 - F 31 DFFE + 0 2 1 0 |DIANTI:28|:38
- 7 - F 25 DFFE + 1 3 1 1 |DIANTI:28|:40
- 8 - F 31 DFFE + 0 3 1 0 |DIANTI:28|:42
- 5 - F 31 DFFE + 1 2 1 0 |DIANTI:28|:44
- 8 - E 16 DFFE + 0 1 1 0 |DIANTI:28|:46
- 1 - E 15 DFFE + 0 1 1 0 |DIANTI:28|:48
- 4 - E 08 DFFE + 0 1 1 0 |DIANTI:28|:50
- 1 - E 35 DFFE + 0 1 1 0 |DIANTI:28|:52
- 7 - E 32 DFFE + 0 1 1 0 |DIANTI:28|:54
- 6 - E 23 DFFE + 0 1 1 0 |DIANTI:28|:56
- 1 - E 16 DFFE + 0 1 1 0 |DIANTI:28|:58
- 4 - E 26 DFFE + 0 1 1 0 |DIANTI:28|:60
- 8 - E 08 DFFE + 0 1 1 0 |DIANTI:28|:62
- 6 - E 35 DFFE + 0 1 1 0 |DIANTI:28|:64
- 6 - E 32 DFFE + 0 1 1 0 |DIANTI:28|:66
- 1 - E 26 DFFE + 0 1 1 0 |DIANTI:28|:68
- 5 - E 16 DFFE + 0 1 1 0 |DIANTI:28|:70
- 4 - E 15 DFFE + 0 1 1 0 |DIANTI:28|:72
- 3 - E 08 DFFE + 0 1 1 0 |DIANTI:28|:74
- 2 - E 35 DFFE + 0 1 1 0 |DIANTI:28|:76
- 1 - E 32 DFFE + 0 1 1 0 |DIANTI:28|:78
- 4 - E 34 DFFE + 0 1 1 0 |DIANTI:28|:80
- 6 - A 22 DFFE + 1 2 1 0 |DIANTI:28|:82
- 1 - F 13 DFFE + 0 1 1 0 |DIANTI:28|:84
- 5 - E 26 DFFE + 2 0 1 0 |DIANTI:28|:86
- 5 - A 27 DFFE + 0 3 1 0 |DIANTI:28|:88
- 5 - A 35 DFFE + 0 3 1 0 |DIANTI:28|:90
- 3 - A 36 DFFE + 0 3 0 6 |DIANTI:28|q12 (|DIANTI:28|:92)
- 3 - A 29 DFFE + 0 3 0 6 |DIANTI:28|q11 (|DIANTI:28|:93)
- 6 - A 35 DFFE + 0 4 0 9 |DIANTI:28|q10 (|DIANTI:28|:94)
- 7 - A 33 DFFE + 1 2 0 1 |DIANTI:28|q22 (|DIANTI:28|:95)
- 5 - A 22 DFFE + 1 3 0 4 |DIANTI:28|q21 (|DIANTI:28|:96)
- 8 - A 33 DFFE + 1 2 0 4 |DIANTI:28|q20 (|DIANTI:28|:97)
- 3 - E 15 DFFE + 0 1 0 32 |DIANTI:28|q (|DIANTI:28|:98)
- 1 - E 31 DFFE + 2 1 0 14 |DIANTI:28|opendoor (|DIANTI:28|:99)
- 4 - A 33 AND2 s 0 4 0 1 |DIANTI:28|en_up~1 (|DIANTI:28|~100~1)
- 5 - E 34 DFFE + 0 3 0 8 |DIANTI:28|en_up (|DIANTI:28|:100)
- 1 - A 27 DFFE + 0 3 0 27 |DIANTI:28|updown (|DIANTI:28|:101)
- 1 - A 29 DFFE + 0 3 0 6 |DIANTI:28|en_dw (|DIANTI:28|:102)
- 3 - E 34 DFFE + 1 2 0 4 |DIANTI:28|d11 (|DIANTI:28|:103)
- 5 - E 23 DFFE + 1 2 0 4 |DIANTI:28|c_u11 (|DIANTI:28|:104)
- 2 - E 16 DFFE + 0 3 0 9 |DIANTI:28|dd_cc5 (|DIANTI:28|:105)
- 8 - E 15 DFFE + 0 3 0 7 |DIANTI:28|dd_cc4 (|DIANTI:28|:106)
- 6 - E 08 DFFE + 0 3 0 2 |DIANTI:28|dd_cc3 (|DIANTI:28|:107)
- 8 - E 35 DFFE + 0 3 0 4 |DIANTI:28|dd_cc2 (|DIANTI:28|:108)
- 8 - E 32 DFFE + 0 3 0 3 |DIANTI:28|dd_cc1 (|DIANTI:28|:109)
- 2 - E 31 DFFE + 0 3 0 1 |DIANTI:28|dd_cc0 (|DIANTI:28|:110)
- 1 - E 33 DFFE + 1 2 0 5 |DIANTI:28|d22 (|DIANTI:28|:111)
- 3 - E 33 DFFE + 0 3 0 3 |DIANTI:28|c_u22 (|DIANTI:28|:112)
- 5 - E 29 DFFE + 0 3 0 3 |DIANTI:28|c_d22 (|DIANTI:28|:113)
- 8 - E 29 DFFE + 0 3 0 5 |DIANTI:28|d33 (|DIANTI:28|:114)
- 1 - E 22 DFFE + 1 2 0 3 |DIANTI:28|c_u33 (|DIANTI:28|:115)
- 3 - E 29 DFFE + 2 2 0 4 |DIANTI:28|c_d33 (|DIANTI:28|:116)
- 3 - E 17 DFFE + 1 2 0 5 |DIANTI:28|d44 (|DIANTI:28|:117)
- 4 - E 05 DFFE + 1 2 0 3 |DIANTI:28|c_u44 (|DIANTI:28|:118)
- 3 - E 10 DFFE + 1 2 0 3 |DIANTI:28|c_d44 (|DIANTI:28|:119)
- 2 - E 17 DFFE + 2 2 0 6 |DIANTI:28|d55 (|DIANTI:28|:120)
- 6 - E 05 DFFE + 2 2 0 4 |DIANTI:28|c_u55 (|DIANTI:28|:121)
- 7 - E 10 DFFE + 1 2 0 3 |DIANTI:28|c_d55 (|DIANTI:28|:122)
- 6 - E 17 DFFE + 0 3 0 3 |DIANTI:28|d66 (|DIANTI:28|:123)
- 1 - E 10 DFFE + 0 3 0 3 |DIANTI:28|c_d66 (|DIANTI:28|:124)
- 4 - E 16 DFFE + 0 3 0 2 |DIANTI:28|dd5 (|DIANTI:28|:125)
- 6 - E 15 DFFE + 0 3 0 2 |DIANTI:28|dd4 (|DIANTI:28|:126)
- 2 - E 08 DFFE + 0 3 0 2 |DIANTI:28|dd3 (|DIANTI:28|:127)
- 4 - E 35 DFFE + 0 3 0 2 |DIANTI:28|dd2 (|DIANTI:28|:128)
- 3 - E 32 DFFE + 0 3 0 2 |DIANTI:28|dd1 (|DIANTI:28|:129)
- 8 - E 34 DFFE + 0 3 0 2 |DIANTI:28|dd0 (|DIANTI:28|:130)
- 7 - E 16 DFFE + 2 1 0 2 |DIANTI:28|cc_u5 (|DIANTI:28|:131)
- 7 - E 15 DFFE + 0 3 0 2 |DIANTI:28|cc_u4 (|DIANTI:28|:132)
- 7 - E 08 DFFE + 0 3 0 2 |DIANTI:28|cc_u3 (|DIANTI:28|:133)
- 7 - E 35 DFFE + 0 3 0 2 |DIANTI:28|cc_u2 (|DIANTI:28|:134)
- 5 - E 32 DFFE + 0 3 0 2 |DIANTI:28|cc_u1 (|DIANTI:28|:135)
- 4 - E 23 DFFE + 0 3 0 2 |DIANTI:28|cc_u0 (|DIANTI:28|:136)
- 6 - E 16 DFFE + 0 3 0 2 |DIANTI:28|cc_d5 (|DIANTI:28|:137)
- 3 - E 26 DFFE + 0 3 0 2 |DIANTI:28|cc_d4 (|DIANTI:28|:138)
- 5 - E 08 DFFE + 0 3 0 2 |DIANTI:28|cc_d3 (|DIANTI:28|:139)
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