yle270.npl

YLP270开发板光盘附带的cpld逻辑试验

JDF G
// Created by Project Navigator ver 1.0
PROJECT YLE270
DESIGN yle270
DEVFAM xc9500xl
DEVFAMTIME 1153830192
DEVICE xc9536xl
DEVICETIME 1153830192
DEVPKG VQ44
DEVPKGTIME 1153830192
DEVSPEED -10
DEVSPEEDTIME 1153830192
DEVTOPLEVELMODULETYPE HDL
TOPLEVELMODULETYPETIME 0
DEVSYNTHESISTOOL XST (VHDL/Verilog)
SYNTHESISTOOLTIME 0
DEVSIMULATOR Other
SIMULATORTIME 0
DEVGENERATEDSIMULATIONMODEL VHDL
GENERATEDSIMULATIONMODELTIME 0
SOURCE YLE270.vhdl
DEPASSOC yle270_dev lock_pin.ucf
[Normal]
p_CPLDFitterminate=xstvhd, 9500xl, VHDL.t_go, 1153884602, Float
xcpldFitDesPrgOption=xstvhd, 9500xl, VHDL.t_go, 1153881187, 0x20060726
[STRATEGY-LIST]
Normal=True