yle270_dev.rpt

YLP270开发板光盘附带的cpld逻辑试验

(unused)              0       0     0   5     FB2_18              (b)     

Signals Used by Logic in Function Block
  1: B_nCS0             6: B_nPCE1           11: B_nPREG 
  2: B_nCS1             7: B_nPCE2           12: B_nPWE 
  3: B_nCS2             8: B_nPIOR           13: B_nRESET 
  4: B_nCS3             9: B_nPIOW           14: CF_IORDY 
  5: B_nCS5            10: B_nPOE            15: IDE_IORDY 

Signal                        1         2         3         4 Signals FB
Name                0----+----0----+----0----+----0----+----0 Used    Inputs
nPWAIT               ........................................ 0       0
BUF_EN               .XXXX................................... 4       4
USR_DEF<5>           X....XXXXXXXXXX......................... 11      11
USR_DEF<4>           ........................................ 0       0
USR_DEF<3>           ........................................ 0       0
                    0----+----1----+----2----+----3----+----4
                              0         0         0         0
Legend:
Total Pt     - Total product terms used by the macrocell signal
Imp Pt       - Product terms imported from other macrocells
Exp Pt       - Product terms exported to other macrocells
               in direction shown
Unused Pt    - Unused local product terms remaining in macrocell
Loc          - Location where logic was mapped in device
Pwr Mode     - Macrocell power mode
Pin Type/Use - I  - Input             GCK - Global Clock
               O  - Output            GTS - Global Output Enable
              (b) - Buried macrocell  GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
    The number of Signals Used may exceed the number of FB Inputs Used due
    to wire-ANDing in the switch matrix.
;;-----------------------------------------------------------------;;
; Implemented Equations.


BUF_DIR <= B_nOE;


BUF_EN <= (B_nCS5 AND B_nCS3 AND B_nCS2 AND B_nCS1);


CF_nCS0 <= NOT ((NOT B_nCS3 AND B_A16));


CF_nCS1 <= NOT ((NOT B_nCS3 AND NOT B_A16));


CF_nOE <= NOT ((NOT B_nCS3 AND NOT B_nOE));


CF_nWE <= NOT ((NOT B_nCS3 AND NOT B_nWE));


IDE_DIOR <= NOT ((NOT B_nCS1 AND NOT B_nOE));


IDE_DIOW <= NOT ((NOT B_nCS1 AND NOT B_nWE));


nWAIT_I <= '0';
nWAIT <= nWAIT_I when nWAIT_OE = '1' else 'Z';
nWAIT_OE <= '0';


nPWAIT_I <= '0';
nPWAIT <= nPWAIT_I when nPWAIT_OE = '1' else 'Z';
nPWAIT_OE <= '0';


USR_DEF(1) <= '0';


USR_DEF(0) <= '0';


USR_DEF(4) <= '1';


USR_DEF(3) <= '1';


USR_DEF(2) <= '1';


USR_DEF(5) <= NOT ((NOT B_nPWE AND NOT B_nPREG AND NOT B_nPOE AND NOT B_nPIOW AND NOT B_nPIOR AND 
	NOT B_nPCE2 AND NOT B_nPCE1 AND NOT B_nCS0 AND NOT IDE_IORDY AND NOT CF_IORDY AND 
	NOT B_nRESET));

Register Legend:
 FDCPE (Q,D,C,CLR,PRE,CE); 
 FTCPE (Q,D,C,CLR,PRE,CE); 
 LDCP  (Q,D,G,CLR,PRE); 

****************************  Device Pin Out ****************************

Device : XC9536XL-10-VQ44


   -----------------------------------  
  /44 43 42 41 40 39 38 37 36 35 34 33 \
 | 1                                32 | 
 | 2                                31 | 
 | 3                                30 | 
 | 4                                29 | 
 | 5         XC9536XL-10-VQ44       28 | 
 | 6                                27 | 
 | 7                                26 | 
 | 8                                25 | 
 | 9                                24 | 
 | 10                               23 | 
 | 11                               22 | 
 \ 12 13 14 15 16 17 18 19 20 21 22 23 /
   -----------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 B_nPREG                          23 B_nPIOR                       
  2 IDE_IORDY                        24 TDO                           
  3 CF_IORDY                         25 GND                           
  4 GND                              26 VCC                           
  5 CF_nOE                           27 B_nPCE1                       
  6 CF_nWE                           28 B_nCS1                        
  7 CF_nCS0                          29 B_nCS2                        
  8 CF_nCS1                          30 B_nCS3                        
  9 TDI                              31 B_nPCE2                       
 10 TMS                              32 B_nCS5                        
 11 TCK                              33 B_nPWE                        
 12 IDE_DIOW                         34 B_nWE                         
 13 IDE_DIOR                         35 VCC                           
 14 USR_DEF<0>                       36 B_nOE                         
 15 VCC                              37 BUF_EN                        
 16 USR_DEF<1>                       38 B_nRESET                      
 17 GND                              39 nPWAIT                        
 18 USR_DEF<2>                       40 nWAIT                         
 19 USR_DEF<3>                       41 B_A16                         
 20 USR_DEF<4>                       42 BUF_DIR                       
 21 USR_DEF<5>                       43 B_nCS0                        
 22 B_nPOE                           44 B_nPIOW                       


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
         PE   = Port Enable pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc9536xl-10-VQ44
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Set Unused I/O Pin Termination              : FLOAT
Set I/O Pin Termination                     : FLOAT
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
Input Limit                                 : 54
Pterm Limit                                 : 25