📄 yle270_dev.rpt
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cpldfit: version G.28 Xilinx Inc.
Fitter Report
Design Name: yle270_dev Date: 8- 2-2006, 6:09PM
Device Used: XC9536XL-10-VQ44
Fitting Status: Successful
**************************** Resource Summary ****************************
Macrocells Product Terms Registers Pins Function Block
Used Used Used Used Inputs Used
16 /36 ( 44%) 9 /180 ( 5%) 0 /36 ( 0%) 34 /34 (100%) 20 /108 ( 19%)
PIN RESOURCES:
Signal Type Required Mapped | Pin Type Used Remaining
------------------------------------|---------------------------------------
Input : 18 18 | I/O : 28 0
Output : 16 16 | GCK/IO : 3 0
Bidirectional : 0 0 | GTS/IO : 2 0
GCK : 0 0 | GSR/IO : 1 0
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 34 34
MACROCELL RESOURCES:
Total Macrocells Available 36
Registered Macrocells 0
Non-registered Macrocell driving I/O 16
GLOBAL RESOURCES:
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
POWER DATA:
There are 16 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
There are a total of 16 macrocells used (MC).
End of Resource Summary
*************** Summary of Required Resources ******************
** LOGIC **
Signal Total Signals Loc Pwr Slew Pin Pin Pin Reg Init
Name Pt Used Mode Rate # Type Use State
BUF_DIR 1 1 FB1_4 STD FAST 42 I/O O
BUF_EN 1 4 FB2_4 STD FAST 37 I/O O
CF_nCS0 1 2 FB1_11 STD SLOW 7 I/O O
CF_nCS1 1 2 FB1_12 STD SLOW 8 I/O O
CF_nOE 1 2 FB1_9 STD FAST 5 I/O O
CF_nWE 1 2 FB1_10 STD FAST 6 I/O O
IDE_DIOR 1 2 FB1_14 STD FAST 13 I/O O
IDE_DIOW 1 2 FB1_13 STD FAST 12 I/O O
USR_DEF<0> 0 0 FB1_15 STD SLOW 14 I/O O
USR_DEF<1> 0 0 FB1_16 STD SLOW 16 I/O O
USR_DEF<2> 0 0 FB1_17 STD SLOW 18 I/O O
USR_DEF<3> 0 0 FB2_17 STD SLOW 19 I/O O
USR_DEF<4> 0 0 FB2_16 STD SLOW 20 I/O O
USR_DEF<5> 1 11 FB2_15 STD SLOW 21 I/O O
nPWAIT 0 0 FB2_1 STD FAST 39 I/O O
nWAIT 0 0 FB1_1 STD FAST 40 I/O O
** INPUTS **
Signal Loc Pin Pin Pin
Name # Type Use
B_A16 FB1_2 41 I/O I
B_nCS0 FB1_3 43 GCK/I/O I
B_nCS1 FB2_11 28 I/O I
B_nCS2 FB2_10 29 I/O I
B_nCS3 FB2_9 30 I/O I
B_nCS5 FB2_7 32 I/O I
B_nOE FB2_3 36 GTS/I/O I
B_nPCE1 FB2_12 27 I/O I
B_nPCE2 FB2_8 31 I/O I
B_nPIOR FB2_13 23 I/O I
B_nPIOW FB1_5 44 GCK/I/O I
B_nPOE FB2_14 22 I/O I
B_nPREG FB1_7 1 GCK/I/O I
B_nPWE FB2_6 33 GSR/I/O I
B_nRESET FB2_2 38 I/O I
B_nWE FB2_5 34 GTS/I/O I
CF_IORDY FB1_8 3 I/O I
IDE_IORDY FB1_6 2 I/O I
End of Resources
*********************Function Block Resource Summary***********************
Function # of FB Inputs Signals Total O/IO IO
Block Macrocells Used Used Pt Used Req Avail
FB1 11 5 5 7 11/0 17
FB2 5 15 15 2 5/0 17
---- ----- ----- -----
16 9 16/0 34
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 5/49
Number of signals used by logic mapping into function block: 5
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
nWAIT 0 0 0 5 FB1_1 STD 40 I/O O
(unused) 0 0 0 5 FB1_2 41 I/O I
(unused) 0 0 0 5 FB1_3 43 GCK/I/O I
BUF_DIR 1 0 0 4 FB1_4 STD 42 I/O O
(unused) 0 0 0 5 FB1_5 44 GCK/I/O I
(unused) 0 0 0 5 FB1_6 2 I/O I
(unused) 0 0 0 5 FB1_7 1 GCK/I/O I
(unused) 0 0 0 5 FB1_8 3 I/O I
CF_nOE 1 0 0 4 FB1_9 STD 5 I/O O
CF_nWE 1 0 0 4 FB1_10 STD 6 I/O O
CF_nCS0 1 0 0 4 FB1_11 STD 7 I/O O
CF_nCS1 1 0 0 4 FB1_12 STD 8 I/O O
IDE_DIOW 1 0 0 4 FB1_13 STD 12 I/O O
IDE_DIOR 1 0 0 4 FB1_14 STD 13 I/O O
USR_DEF<0> 0 0 0 5 FB1_15 STD 14 I/O O
USR_DEF<1> 0 0 0 5 FB1_16 STD 16 I/O O
USR_DEF<2> 0 0 0 5 FB1_17 STD 18 I/O O
(unused) 0 0 0 5 FB1_18 (b)
Signals Used by Logic in Function Block
1: B_nOE 3: B_nCS1 5: B_nWE
2: B_A16 4: B_nCS3
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
nWAIT ........................................ 0 0
BUF_DIR X....................................... 1 1
CF_nOE X..X.................................... 2 2
CF_nWE ...XX................................... 2 2
CF_nCS0 .X.X.................................... 2 2
CF_nCS1 .X.X.................................... 2 2
IDE_DIOW ..X.X................................... 2 2
IDE_DIOR X.X..................................... 2 2
USR_DEF<0> ........................................ 0 0
USR_DEF<1> ........................................ 0 0
USR_DEF<2> ........................................ 0 0
0----+----1----+----2----+----3----+----4
0 0 0 0
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pwr Mode - Macrocell power mode
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs Used due
to wire-ANDing in the switch matrix.
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 15/39
Number of signals used by logic mapping into function block: 15
Signal Total Imp Exp Unused Loc Pwr Pin Pin Pin
Name Pt Pt Pt Pt Mode # Type Use
nPWAIT 0 0 0 5 FB2_1 STD 39 I/O O
(unused) 0 0 0 5 FB2_2 38 I/O I
(unused) 0 0 0 5 FB2_3 36 GTS/I/O I
BUF_EN 1 0 0 4 FB2_4 STD 37 I/O O
(unused) 0 0 0 5 FB2_5 34 GTS/I/O I
(unused) 0 0 0 5 FB2_6 33 GSR/I/O I
(unused) 0 0 0 5 FB2_7 32 I/O I
(unused) 0 0 0 5 FB2_8 31 I/O I
(unused) 0 0 0 5 FB2_9 30 I/O I
(unused) 0 0 0 5 FB2_10 29 I/O I
(unused) 0 0 0 5 FB2_11 28 I/O I
(unused) 0 0 0 5 FB2_12 27 I/O I
(unused) 0 0 0 5 FB2_13 23 I/O I
(unused) 0 0 0 5 FB2_14 22 I/O I
USR_DEF<5> 1 0 0 4 FB2_15 STD 21 I/O O
USR_DEF<4> 0 0 0 5 FB2_16 STD 20 I/O O
USR_DEF<3> 0 0 0 5 FB2_17 STD 19 I/O O
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