yle270_dev.syr

YLP270开发板光盘附带的cpld逻辑试验

Release 6.2i - xst G.28
Copyright (c) 1995-2004 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to __projnav
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--> Parameter xsthdpdir set to ./xst
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--> Reading design: yle270_dev.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) HDL Analysis
  4) HDL Synthesis
  5) Advanced HDL Synthesis
     5.1) HDL Synthesis Report
  6) Low Level Synthesis
  7) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : yle270_dev.prj
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO
Verilog Include Directory          : 

---- Target Parameters
Output File Name                   : yle270_dev
Output Format                      : NGC
Target Device                      : xc9500xl

---- Source Options
Top Module Name                    : yle270_dev
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
Equivalent register Removal        : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : _
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : yle270_dev.lso
verilog2001                        : YES
Clock Enable                       : YES
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file D:/qjy/PLD/YLE270.vhdl in Library work.
Architecture decode of Entity yle270_dev is up to date.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <yle270_dev> (Architecture <decode>).
Entity <yle270_dev> analyzed. Unit <yle270_dev> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Synthesizing Unit <yle270_dev>.
    Related source file is D:/qjy/PLD/YLE270.vhdl.
    Found 1-bit tristate buffer for signal <nWAIT>.
    Found 1-bit tristate buffer for signal <nPWAIT>.
    Summary:
	inferred   2 Tristate(s).
Unit <yle270_dev> synthesized.


=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================

Advanced RAM inference ...
Advanced multiplier inference ...
Dynamic shift register inference ...

=========================================================================
HDL Synthesis Report

Macro Statistics
# Tristates                        : 2
 1-bit tristate buffer             : 2

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <yle270_dev> ...

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : yle270_dev.ngr
Top Level Output File Name         : yle270_dev
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : xc9500xl
Macro Preserve                     : YES
XOR Preserve                       : YES
Clock Enable                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 34

Macro Statistics :
# Tristates                        : 2
#      1-bit tristate buffer       : 2

Cell Usage :
# BELS                             : 41
#      AND2                        : 7
#      AND3                        : 1
#      AND4                        : 1
#      AND8                        : 1
#      GND                         : 1
#      INV                         : 29
#      VCC                         : 1
# IO Buffers                       : 34
#      IBUF                        : 18
#      OBUF                        : 14
#      OBUFE                       : 2
=========================================================================
CPU : 1.49 / 2.50 s | Elapsed : 2.00 / 3.00 s
 
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Total memory usage is 49708 kilobytes