gdb.tan.qmsg

控制三相步进电机及光电编码器的采集

{ "Info" "ITDB_FULL_TPD_RESULT" "GATEV VIODE_A 8.474 ns Longest " "Info: Longest tpd from source pin \"GATEV\" to destination pin \"VIODE_A\" is 8.474 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns GATEV 1 PIN PIN_70 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_70; Fanout = 2; PIN Node = 'GATEV'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GATEV } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.481 ns) + CELL(0.200 ns) 3.813 ns VIODE_A~0 2 COMB LC_X7_Y3_N7 1 " "Info: 2: + IC(2.481 ns) + CELL(0.200 ns) = 3.813 ns; Loc. = LC_X7_Y3_N7; Fanout = 1; COMB Node = 'VIODE_A~0'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { GATEV VIODE_A~0 } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.339 ns) + CELL(2.322 ns) 8.474 ns VIODE_A 3 PIN PIN_6 0 " "Info: 3: + IC(2.339 ns) + CELL(2.322 ns) = 8.474 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'VIODE_A'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.661 ns" { VIODE_A~0 VIODE_A } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.654 ns ( 43.12 % ) " "Info: Total cell delay = 3.654 ns ( 43.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.820 ns ( 56.88 % ) " "Info: Total interconnect delay = 4.820 ns ( 56.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.474 ns" { GATEV VIODE_A~0 VIODE_A } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.474 ns" { GATEV GATEV~combout VIODE_A~0 VIODE_A } { 0.000ns 0.000ns 2.481ns 2.339ns } { 0.000ns 1.132ns 0.200ns 2.322ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "BOUT AB\[1\] clk 3.641 ns register " "Info: th for register \"BOUT\" (data pin = \"AB\[1\]\", clock pin = \"clk\") is 3.641 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.967 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.967 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns VIODE 2 REG LC_X6_Y3_N7 17 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X6_Y3_N7; Fanout = 17; REG Node = 'VIODE'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk VIODE } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.325 ns) + CELL(0.918 ns) 7.967 ns BOUT 3 REG LC_X7_Y2_N5 1 " "Info: 3: + IC(3.325 ns) + CELL(0.918 ns) = 7.967 ns; Loc. = LC_X7_Y2_N5; Fanout = 1; REG Node = 'BOUT'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.243 ns" { VIODE BOUT } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 273 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 42.36 % ) " "Info: Total cell delay = 3.375 ns ( 42.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.592 ns ( 57.64 % ) " "Info: Total interconnect delay = 4.592 ns ( 57.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.967 ns" { clk VIODE BOUT } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.967 ns" { clk clk~combout VIODE BOUT } { 0.000ns 0.000ns 1.267ns 3.325ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 273 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.547 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.547 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns AB\[1\] 1 PIN PIN_91 10 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_91; Fanout = 10; PIN Node = 'AB\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AB[1] } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.824 ns) + CELL(0.591 ns) 4.547 ns BOUT 2 REG LC_X7_Y2_N5 1 " "Info: 2: + IC(2.824 ns) + CELL(0.591 ns) = 4.547 ns; Loc. = LC_X7_Y2_N5; Fanout = 1; REG Node = 'BOUT'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.415 ns" { AB[1] BOUT } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 273 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 37.89 % ) " "Info: Total cell delay = 1.723 ns ( 37.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.824 ns ( 62.11 % ) " "Info: Total interconnect delay = 2.824 ns ( 62.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.547 ns" { AB[1] BOUT } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.547 ns" { AB[1] AB[1]~combout BOUT } { 0.000ns 0.000ns 2.824ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.967 ns" { clk VIODE BOUT } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.967 ns" { clk clk~combout VIODE BOUT } { 0.000ns 0.000ns 1.267ns 3.325ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.547 ns" { AB[1] BOUT } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.547 ns" { AB[1] AB[1]~combout BOUT } { 0.000ns 0.000ns 2.824ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "108 " "Info: Allocated 108 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 19 15:18:14 2008 " "Info: Processing ended: Sat Jan 19 15:18:14 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}