prev_cmp_gdb.qmsg

控制三相步进电机及光电编码器的采集

{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" {  } {  } 0 0 "Started post-fitting delay annotation" 0 0 "" 0}
{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" {  } {  } 0 0 "Delay annotation completed successfully" 0 0 "" 0}
{ "Warning" "WTAN_SCC_LOOP" "1 " "Warning: Found combinational loop of 1 nodes" { { "Warning" "WTAN_SCC_NODE" "AQR~57 " "Warning: Node \"AQR~57\"" {  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 54 -1 0 } }  } 0 0 "Node \"%1!s!\"" 0 0 "" 0}  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 54 -1 0 } }  } 0 0 "Found combinational loop of %1!d! nodes" 0 0 "" 0}
{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk " "Info: Assuming node \"clk\" is an undefined clock" {  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 12 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "clk" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0} { "Info" "ITAN_NODE_MAP_TO_CLK" "WR " "Info: Assuming node \"WR\" is an undefined clock" {  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 29 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "WR" } } } }  } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0}  } {  } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "TIMECOUNTDJ1 " "Info: Detected ripple clock \"TIMECOUNTDJ1\" as buffer" {  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 45 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "TIMECOUNTDJ1" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0} { "Info" "ITAN_RIPPLE_CLK" "VIODE " "Info: Detected ripple clock \"VIODE\" as buffer" {  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 47 -1 0 } } { "d:/altera/71/quartus/bin/Assignment Editor.qase" "" { Assignment "d:/altera/71/quartus/bin/Assignment Editor.qase" 1 { { 0 "VIODE" } } } }  } 0 0 "Detected ripple clock \"%1!s!\" as buffer" 0 0 "" 0}  } {  } 0 0 "Found %1!d! node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" 0 0 "" 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk register DJCOUNT1\[9\] register DJCOUNT1\[9\] 112.06 MHz 8.924 ns Internal " "Info: Clock \"clk\" has Internal fmax of 112.06 MHz between source register \"DJCOUNT1\[9\]\" and destination register \"DJCOUNT1\[9\]\" (period= 8.924 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.215 ns + Longest register register " "Info: + Longest register to register delay is 8.215 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DJCOUNT1\[9\] 1 REG LC_X3_Y2_N8 3 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X3_Y2_N8; Fanout = 3; REG Node = 'DJCOUNT1\[9\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DJCOUNT1[9] } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 149 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.994 ns) + CELL(0.740 ns) 2.734 ns Equal6~86 2 COMB LC_X3_Y4_N2 1 " "Info: 2: + IC(1.994 ns) + CELL(0.740 ns) = 2.734 ns; Loc. = LC_X3_Y4_N2; Fanout = 1; COMB Node = 'Equal6~86'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.734 ns" { DJCOUNT1[9] Equal6~86 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.363 ns) + CELL(0.200 ns) 5.297 ns Equal6~87 3 COMB LC_X3_Y4_N5 7 " "Info: 3: + IC(2.363 ns) + CELL(0.200 ns) = 5.297 ns; Loc. = LC_X3_Y4_N5; Fanout = 7; COMB Node = 'Equal6~87'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.563 ns" { Equal6~86 Equal6~87 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.857 ns) + CELL(1.061 ns) 8.215 ns DJCOUNT1\[9\] 4 REG LC_X3_Y2_N8 3 " "Info: 4: + IC(1.857 ns) + CELL(1.061 ns) = 8.215 ns; Loc. = LC_X3_Y2_N8; Fanout = 3; REG Node = 'DJCOUNT1\[9\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.918 ns" { Equal6~87 DJCOUNT1[9] } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 149 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.001 ns ( 24.36 % ) " "Info: Total cell delay = 2.001 ns ( 24.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "6.214 ns ( 75.64 % ) " "Info: Total interconnect delay = 6.214 ns ( 75.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.215 ns" { DJCOUNT1[9] Equal6~86 Equal6~87 DJCOUNT1[9] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.215 ns" { DJCOUNT1[9] Equal6~86 Equal6~87 DJCOUNT1[9] } { 0.000ns 1.994ns 2.363ns 1.857ns } { 0.000ns 0.740ns 0.200ns 1.061ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 3.348 ns + Shortest register " "Info: + Shortest clock path from clock \"clk\" to destination register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns DJCOUNT1\[9\] 2 REG LC_X3_Y2_N8 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y2_N8; Fanout = 3; REG Node = 'DJCOUNT1\[9\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk DJCOUNT1[9] } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 149 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk DJCOUNT1[9] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout DJCOUNT1[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 3.348 ns - Longest register " "Info: - Longest clock path from clock \"clk\" to source register is 3.348 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(0.918 ns) 3.348 ns DJCOUNT1\[9\] 2 REG LC_X3_Y2_N8 3 " "Info: 2: + IC(1.267 ns) + CELL(0.918 ns) = 3.348 ns; Loc. = LC_X3_Y2_N8; Fanout = 3; REG Node = 'DJCOUNT1\[9\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.185 ns" { clk DJCOUNT1[9] } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 149 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.081 ns ( 62.16 % ) " "Info: Total cell delay = 2.081 ns ( 62.16 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.267 ns ( 37.84 % ) " "Info: Total interconnect delay = 1.267 ns ( 37.84 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk DJCOUNT1[9] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout DJCOUNT1[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk DJCOUNT1[9] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout DJCOUNT1[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk DJCOUNT1[9] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout DJCOUNT1[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 149 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 149 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.215 ns" { DJCOUNT1[9] Equal6~86 Equal6~87 DJCOUNT1[9] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.215 ns" { DJCOUNT1[9] Equal6~86 Equal6~87 DJCOUNT1[9] } { 0.000ns 1.994ns 2.363ns 1.857ns } { 0.000ns 0.740ns 0.200ns 1.061ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk DJCOUNT1[9] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout DJCOUNT1[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.348 ns" { clk DJCOUNT1[9] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "3.348 ns" { clk clk~combout DJCOUNT1[9] } { 0.000ns 0.000ns 1.267ns } { 0.000ns 1.163ns 0.918ns } "" } }  } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0}
{ "Info" "ITAN_NO_REG2REG_EXIST" "WR " "Info: No valid register-to-register data paths exist for clock \"WR\"" {  } {  } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0}
{ "Info" "ITDB_TSU_RESULT" "DD\[6\] ADDR\[4\] WR 2.734 ns register " "Info: tsu for register \"DD\[6\]\" (data pin = \"ADDR\[4\]\", clock pin = \"WR\") is 2.734 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.128 ns + Longest pin register " "Info: + Longest pin to register delay is 8.128 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns ADDR\[4\] 1 PIN PIN_48 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_48; Fanout = 1; PIN Node = 'ADDR\[4\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { ADDR[4] } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 21 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.545 ns) + CELL(0.511 ns) 4.188 ns Equal2~146 2 COMB LC_X4_Y1_N4 1 " "Info: 2: + IC(2.545 ns) + CELL(0.511 ns) = 4.188 ns; Loc. = LC_X4_Y1_N4; Fanout = 1; COMB Node = 'Equal2~146'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.056 ns" { ADDR[4] Equal2~146 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(0.719 ns) + CELL(0.914 ns) 5.821 ns Equal2~150 3 COMB LC_X4_Y1_N2 8 " "Info: 3: + IC(0.719 ns) + CELL(0.914 ns) = 5.821 ns; Loc. = LC_X4_Y1_N2; Fanout = 8; COMB Node = 'Equal2~150'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "1.633 ns" { Equal2~146 Equal2~150 } "NODE_NAME" } } { "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" "" { Text "d:/altera/71/quartus/libraries/vhdl/synopsys/syn_arit.vhd" 1805 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.064 ns) + CELL(1.243 ns) 8.128 ns DD\[6\] 4 REG LC_X5_Y1_N4 1 " "Info: 4: + IC(1.064 ns) + CELL(1.243 ns) = 8.128 ns; Loc. = LC_X5_Y1_N4; Fanout = 1; REG Node = 'DD\[6\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.307 ns" { Equal2~150 DD[6] } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.800 ns ( 46.75 % ) " "Info: Total cell delay = 3.800 ns ( 46.75 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.328 ns ( 53.25 % ) " "Info: Total interconnect delay = 4.328 ns ( 53.25 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.128 ns" { ADDR[4] Equal2~146 Equal2~150 DD[6] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.128 ns" { ADDR[4] ADDR[4]~combout Equal2~146 Equal2~150 DD[6] } { 0.000ns 0.000ns 2.545ns 0.719ns 1.064ns } { 0.000ns 1.132ns 0.511ns 0.914ns 1.243ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" {  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 141 -1 0 } }  } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "WR destination 5.727 ns - Shortest register " "Info: - Shortest clock path from clock \"WR\" to destination register is 5.727 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns WR 1 CLK PIN_29 8 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_29; Fanout = 8; CLK Node = 'WR'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { WR } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 29 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.677 ns) + CELL(0.918 ns) 5.727 ns DD\[6\] 2 REG LC_X5_Y1_N4 1 " "Info: 2: + IC(3.677 ns) + CELL(0.918 ns) = 5.727 ns; Loc. = LC_X5_Y1_N4; Fanout = 1; REG Node = 'DD\[6\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.595 ns" { WR DD[6] } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 141 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.050 ns ( 35.80 % ) " "Info: Total cell delay = 2.050 ns ( 35.80 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.677 ns ( 64.20 % ) " "Info: Total interconnect delay = 3.677 ns ( 64.20 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.727 ns" { WR DD[6] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.727 ns" { WR WR~combout DD[6] } { 0.000ns 0.000ns 3.677ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.128 ns" { ADDR[4] Equal2~146 Equal2~150 DD[6] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.128 ns" { ADDR[4] ADDR[4]~combout Equal2~146 Equal2~150 DD[6] } { 0.000ns 0.000ns 2.545ns 0.719ns 1.064ns } { 0.000ns 1.132ns 0.511ns 0.914ns 1.243ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "5.727 ns" { WR DD[6] } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "5.727 ns" { WR WR~combout DD[6] } { 0.000ns 0.000ns 3.677ns } { 0.000ns 1.132ns 0.918ns } "" } }  } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clk DJB DJB1~en 12.756 ns register " "Info: tco from clock \"clk\" to destination pin \"DJB\" through register \"DJB1~en\" is 12.756 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk source 7.388 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to source register is 7.388 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns TIMECOUNTDJ1 2 REG LC_X2_Y3_N4 8 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N4; Fanout = 8; REG Node = 'TIMECOUNTDJ1'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk TIMECOUNTDJ1 } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 45 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.746 ns) + CELL(0.918 ns) 7.388 ns DJB1~en 3 REG LC_X5_Y2_N8 1 " "Info: 3: + IC(2.746 ns) + CELL(0.918 ns) = 7.388 ns; Loc. = LC_X5_Y2_N8; Fanout = 1; REG Node = 'DJB1~en'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.664 ns" { TIMECOUNTDJ1 DJB1~en } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 45.68 % ) " "Info: Total cell delay = 3.375 ns ( 45.68 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.013 ns ( 54.32 % ) " "Info: Total interconnect delay = 4.013 ns ( 54.32 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.388 ns" { clk TIMECOUNTDJ1 DJB1~en } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.388 ns" { clk clk~combout TIMECOUNTDJ1 DJB1~en } { 0.000ns 0.000ns 1.267ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" {  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 235 -1 0 } }  } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.992 ns + Longest register pin " "Info: + Longest register to pin delay is 4.992 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns DJB1~en 1 REG LC_X5_Y2_N8 1 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X5_Y2_N8; Fanout = 1; REG Node = 'DJB1~en'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { DJB1~en } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 235 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.670 ns) + CELL(2.322 ns) 4.992 ns DJB 2 PIN PIN_2 0 " "Info: 2: + IC(2.670 ns) + CELL(2.322 ns) = 4.992 ns; Loc. = PIN_2; Fanout = 0; PIN Node = 'DJB'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.992 ns" { DJB1~en DJB } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 24 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns ( 46.51 % ) " "Info: Total cell delay = 2.322 ns ( 46.51 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.670 ns ( 53.49 % ) " "Info: Total interconnect delay = 2.670 ns ( 53.49 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.992 ns" { DJB1~en DJB } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.992 ns" { DJB1~en DJB } { 0.000ns 2.670ns } { 0.000ns 2.322ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.388 ns" { clk TIMECOUNTDJ1 DJB1~en } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.388 ns" { clk clk~combout TIMECOUNTDJ1 DJB1~en } { 0.000ns 0.000ns 1.267ns 2.746ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.992 ns" { DJB1~en DJB } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.992 ns" { DJB1~en DJB } { 0.000ns 2.670ns } { 0.000ns 2.322ns } "" } }  } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0}
{ "Info" "ITDB_FULL_TPD_RESULT" "GATEV VIODE_A 8.474 ns Longest " "Info: Longest tpd from source pin \"GATEV\" to destination pin \"VIODE_A\" is 8.474 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns GATEV 1 PIN PIN_70 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_70; Fanout = 2; PIN Node = 'GATEV'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { GATEV } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 18 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.481 ns) + CELL(0.200 ns) 3.813 ns VIODE_A~0 2 COMB LC_X7_Y3_N7 1 " "Info: 2: + IC(2.481 ns) + CELL(0.200 ns) = 3.813 ns; Loc. = LC_X7_Y3_N7; Fanout = 1; COMB Node = 'VIODE_A~0'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.681 ns" { GATEV VIODE_A~0 } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.339 ns) + CELL(2.322 ns) 8.474 ns VIODE_A 3 PIN PIN_6 0 " "Info: 3: + IC(2.339 ns) + CELL(2.322 ns) = 8.474 ns; Loc. = PIN_6; Fanout = 0; PIN Node = 'VIODE_A'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.661 ns" { VIODE_A~0 VIODE_A } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 27 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.654 ns ( 43.12 % ) " "Info: Total cell delay = 3.654 ns ( 43.12 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.820 ns ( 56.88 % ) " "Info: Total interconnect delay = 4.820 ns ( 56.88 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "8.474 ns" { GATEV VIODE_A~0 VIODE_A } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "8.474 ns" { GATEV GATEV~combout VIODE_A~0 VIODE_A } { 0.000ns 0.000ns 2.481ns 2.339ns } { 0.000ns 1.132ns 0.200ns 2.322ns } "" } }  } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0}
{ "Info" "ITDB_TH_RESULT" "BOUT AB\[1\] clk 3.641 ns register " "Info: th for register \"BOUT\" (data pin = \"AB\[1\]\", clock pin = \"clk\") is 3.641 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk destination 7.967 ns + Longest register " "Info: + Longest clock path from clock \"clk\" to destination register is 7.967 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clk 1 CLK PIN_12 55 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 55; CLK Node = 'clk'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { clk } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 12 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns VIODE 2 REG LC_X6_Y3_N7 17 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X6_Y3_N7; Fanout = 17; REG Node = 'VIODE'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "2.561 ns" { clk VIODE } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 47 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(3.325 ns) + CELL(0.918 ns) 7.967 ns BOUT 3 REG LC_X7_Y2_N5 1 " "Info: 3: + IC(3.325 ns) + CELL(0.918 ns) = 7.967 ns; Loc. = LC_X7_Y2_N5; Fanout = 1; REG Node = 'BOUT'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.243 ns" { VIODE BOUT } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 273 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns ( 42.36 % ) " "Info: Total cell delay = 3.375 ns ( 42.36 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.592 ns ( 57.64 % ) " "Info: Total interconnect delay = 4.592 ns ( 57.64 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.967 ns" { clk VIODE BOUT } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.967 ns" { clk clk~combout VIODE BOUT } { 0.000ns 0.000ns 1.267ns 3.325ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } }  } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 273 -1 0 } }  } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "4.547 ns - Shortest pin register " "Info: - Shortest pin to register delay is 4.547 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns AB\[1\] 1 PIN PIN_91 10 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_91; Fanout = 10; PIN Node = 'AB\[1\]'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "" { AB[1] } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 22 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_NODE_DELAY" "IC(2.824 ns) + CELL(0.591 ns) 4.547 ns BOUT 2 REG LC_X7_Y2_N5 1 " "Info: 2: + IC(2.824 ns) + CELL(0.591 ns) = 4.547 ns; Loc. = LC_X7_Y2_N5; Fanout = 1; REG Node = 'BOUT'" {  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "3.415 ns" { AB[1] BOUT } "NODE_NAME" } } { "GDB.vhd" "" { Text "C:/Documents and Settings/dell/桌面/编码器/复件 CPLD最终/GDB.vhd" 273 -1 0 } }  } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.723 ns ( 37.89 % ) " "Info: Total cell delay = 1.723 ns ( 37.89 % )" {  } {  } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.824 ns ( 62.11 % ) " "Info: Total interconnect delay = 2.824 ns ( 62.11 % )" {  } {  } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.547 ns" { AB[1] BOUT } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.547 ns" { AB[1] AB[1]~combout BOUT } { 0.000ns 0.000ns 2.824ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0}  } { { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "7.967 ns" { clk VIODE BOUT } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "7.967 ns" { clk clk~combout VIODE BOUT } { 0.000ns 0.000ns 1.267ns 3.325ns } { 0.000ns 1.163ns 1.294ns 0.918ns } "" } } { "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" { Floorplan "d:/altera/71/quartus/bin/TimingClosureFloorplan.fld" "" "4.547 ns" { AB[1] BOUT } "NODE_NAME" } } { "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/71/quartus/bin/Technology_Viewer.qrui" "4.547 ns" { AB[1] AB[1]~combout BOUT } { 0.000ns 0.000ns 2.824ns } { 0.000ns 1.132ns 0.591ns } "" } }  } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0}
{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 4 s Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "107 " "Info: Allocated 107 megabytes of memory during processing" {  } {  } 0 0 "Allocated %1!s! megabytes of memory during processing" 0 0 "" 0} { "Info" "IQEXE_END_BANNER_TIME" "Sat Jan 19 15:16:28 2008 " "Info: Processing ended: Sat Jan 19 15:16:28 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}
{ "Info" "IFLOW_ERROR_COUNT" "Full Compilation 0 s 12 s " "Info: Quartus II Full Compilation was successful. 0 errors, 12 warnings" {  } {  } 0 0 "Quartus II %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0}