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📄 xc.rpt

📁 基于CPLD XC95018开发的一段VHDL代码
💻 RPT
📖 第 1 页 / 共 4 页
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p0a_T(4) <= ((NOT a12k AND NOT a11k AND p0k(4).PIN AND NOT kwrdata(4).LFBK)
	OR (NOT a12k AND NOT a11k AND NOT p0k(4).PIN AND kwrdata(4).LFBK));
p0a(4) <= p0a_I(4) when p0a_OE(4) = '1' else 'Z';
p0a_OE(4) <= (a15a AND NOT rda);

FTCPE_p0a5: FTCPE port map (p0a_I(5),p0a_T(5),NOT kwrdatdo(7)/kwrdatdo(7)_CLKF__$INT,'0','0');
p0a_T(5) <= ((NOT a12k AND NOT a11k AND p0k(5).PIN AND NOT kwrdata(5).LFBK)
	OR (NOT a12k AND NOT a11k AND NOT p0k(5).PIN AND kwrdata(5).LFBK));
p0a(5) <= p0a_I(5) when p0a_OE(5) = '1' else 'Z';
p0a_OE(5) <= (a15a AND NOT rda);

FTCPE_p0a6: FTCPE port map (p0a_I(6),p0a_T(6),NOT kwrdatdo(7)/kwrdatdo(7)_CLKF__$INT,'0','0');
p0a_T(6) <= ((NOT a12k AND NOT a11k AND p0k(6).PIN AND NOT kwrdata(6).LFBK)
	OR (NOT a12k AND NOT a11k AND NOT p0k(6).PIN AND kwrdata(6).LFBK));
p0a(6) <= p0a_I(6) when p0a_OE(6) = '1' else 'Z';
p0a_OE(6) <= (a15a AND NOT rda);

FTCPE_p0a7: FTCPE port map (p0a_I(7),p0a_T(7),NOT kwrdatdo(7)/kwrdatdo(7)_CLKF__$INT,'0','0');
p0a_T(7) <= ((NOT a12k AND NOT a11k AND p0k(7).PIN AND NOT kwrdata(7).LFBK)
	OR (NOT a12k AND NOT a11k AND NOT p0k(7).PIN AND kwrdata(7).LFBK));
p0a(7) <= p0a_I(7) when p0a_OE(7) = '1' else 'Z';
p0a_OE(7) <= (a15a AND NOT rda);


p0d_I(0) <= ((kwrdatdo(0) AND NOT a14d)
	OR (kwrdatdh(0) AND a13d AND a14d)
	OR (kwrdatdl(0) AND NOT a13d AND a14d));
p0d(0) <= p0d_I(0) when p0d_OE(0) = '1' else 'Z';
p0d_OE(0) <= (a15d AND NOT rdd);


p0d_I(1) <= ((kwrdatdo(1) AND NOT a14d)
	OR (kwrdatdh(1) AND a13d AND a14d)
	OR (kwrdatdl(1) AND NOT a13d AND a14d));
p0d(1) <= p0d_I(1) when p0d_OE(1) = '1' else 'Z';
p0d_OE(1) <= (a15d AND NOT rdd);


p0d_I(2) <= ((NOT a14d AND kwrdatdo(2).LFBK)
	OR (a13d AND a14d AND kwrdatdh(2).LFBK)
	OR (NOT a13d AND a14d AND kwrdatdl(2).LFBK));
p0d(2) <= p0d_I(2) when p0d_OE(2) = '1' else 'Z';
p0d_OE(2) <= (a15d AND NOT rdd);


p0d_I(3) <= ((kwrdatdo(3) AND NOT a14d)
	OR (kwrdatdl(3) AND NOT a13d AND a14d)
	OR (a13d AND a14d AND kwrdatdh(3).LFBK));
p0d(3) <= p0d_I(3) when p0d_OE(3) = '1' else 'Z';
p0d_OE(3) <= (a15d AND NOT rdd);


p0d_I(4) <= ((NOT a14d AND kwrdatdo(4).LFBK)
	OR (kwrdatdh(4) AND a13d AND a14d)
	OR (kwrdatdl(4) AND NOT a13d AND a14d));
p0d(4) <= p0d_I(4) when p0d_OE(4) = '1' else 'Z';
p0d_OE(4) <= (a15d AND NOT rdd);


p0d_I(5) <= ((NOT a14d AND kwrdatdo(5).LFBK)
	OR (kwrdatdh(5) AND a13d AND a14d)
	OR (kwrdatdl(5) AND NOT a13d AND a14d));
p0d(5) <= p0d_I(5) when p0d_OE(5) = '1' else 'Z';
p0d_OE(5) <= (a15d AND NOT rdd);


p0d_I(6) <= ((NOT a14d AND kwrdatdo(6).LFBK)
	OR (kwrdatdh(6) AND a13d AND a14d)
	OR (kwrdatdl(6) AND NOT a13d AND a14d));
p0d(6) <= p0d_I(6) when p0d_OE(6) = '1' else 'Z';
p0d_OE(6) <= (a15d AND NOT rdd);


p0d_I(7) <= ((NOT a14d AND kwrdatdo(7).LFBK)
	OR (kwrdatdh(7) AND a13d AND a14d)
	OR (kwrdatdl(7) AND NOT a13d AND a14d));
p0d(7) <= p0d_I(7) when p0d_OE(7) = '1' else 'Z';
p0d_OE(7) <= (a15d AND NOT rdd);


p0k_I(0) <= ((a12k AND dwrdat(0))
	OR (NOT a12k AND a11k AND awrdath(0))
	OR (NOT a12k AND NOT a11k AND awrdatl(0)));
p0k(0) <= p0k_I(0) when p0k_OE(0) = '1' else 'Z';
p0k_OE(0) <= (NOT rdk AND a15k AND a14k);


p0k_I(1) <= ((a12k AND dwrdat(1))
	OR (NOT a12k AND a11k AND awrdath(1))
	OR (NOT a12k AND NOT a11k AND awrdatl(1)));
p0k(1) <= p0k_I(1) when p0k_OE(1) = '1' else 'Z';
p0k_OE(1) <= (NOT rdk AND a15k AND a14k);


p0k_I(2) <= ((a12k AND dwrdat(2))
	OR (NOT a12k AND a11k AND awrdath(2).LFBK)
	OR (NOT a12k AND NOT a11k AND awrdatl(2).LFBK));
p0k(2) <= p0k_I(2) when p0k_OE(2) = '1' else 'Z';
p0k_OE(2) <= (NOT rdk AND a15k AND a14k);


p0k_I(3) <= ((a12k AND dwrdat(3))
	OR (NOT a12k AND a11k AND awrdath(3))
	OR (NOT a12k AND NOT a11k AND awrdatl(3)));
p0k(3) <= p0k_I(3) when p0k_OE(3) = '1' else 'Z';
p0k_OE(3) <= (NOT rdk AND a15k AND a14k);


p0k_I(4) <= ((a12k AND dwrdat(4))
	OR (NOT a12k AND a11k AND awrdath(4))
	OR (NOT a12k AND NOT a11k AND awrdatl(4)));
p0k(4) <= p0k_I(4) when p0k_OE(4) = '1' else 'Z';
p0k_OE(4) <= (NOT rdk AND a15k AND a14k);


p0k_I(5) <= ((a12k AND dwrdat(5))
	OR (NOT a12k AND a11k AND awrdath(5))
	OR (NOT a12k AND NOT a11k AND awrdatl(5)));
p0k(5) <= p0k_I(5) when p0k_OE(5) = '1' else 'Z';
p0k_OE(5) <= (NOT rdk AND a15k AND a14k);


p0k_I(6) <= ((a12k AND dwrdat(6))
	OR (NOT a12k AND a11k AND awrdath(6))
	OR (NOT a12k AND NOT a11k AND awrdatl(6)));
p0k(6) <= p0k_I(6) when p0k_OE(6) = '1' else 'Z';
p0k_OE(6) <= (NOT rdk AND a15k AND a14k);


p0k_I(7) <= ((a12k AND dwrdat(7))
	OR (NOT a12k AND a11k AND awrdath(7))
	OR (NOT a12k AND NOT a11k AND awrdatl(7)));
p0k(7) <= p0k_I(7) when p0k_OE(7) = '1' else 'Z';
p0k_OE(7) <= (NOT rdk AND a15k AND a14k);

Register Legend:
 FDCPE (Q,D,C,CLR,PRE); 
 FTCPE (Q,D,C,CLR,PRE); 
 LDCP  (Q,D,G,CLR,PRE); 

******************************  Device Pin Out *****************************

Device : XC95108-7-PC84


   --------------------------------------------------------------  
  /11 10 9  8  7  6  5  4  3  2  1  84 83 82 81 80 79 78 77 76 75 \
 | 12                                                          74 | 
 | 13                                                          73 | 
 | 14                                                          72 | 
 | 15                                                          71 | 
 | 16                                                          70 | 
 | 17                                                          69 | 
 | 18                                                          68 | 
 | 19                                                          67 | 
 | 20                                                          66 | 
 | 21                       XC95108-7-PC84                     65 | 
 | 22                                                          64 | 
 | 23                                                          63 | 
 | 24                                                          62 | 
 | 25                                                          61 | 
 | 26                                                          60 | 
 | 27                                                          59 | 
 | 28                                                          58 | 
 | 29                                                          57 | 
 | 30                                                          56 | 
 | 31                                                          55 | 
 | 32                                                          54 | 
 \ 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 /
   --------------------------------------------------------------  


Pin Signal                         Pin Signal                        
No. Name                           No. Name                          
  1 ckey                             43 p0d<5>                        
  2 TIE                              44 p0d<4>                        
  3 TIE                              45 p0d<3>                        
  4 TIE                              46 p0d<2>                        
  5 TIE                              47 p0d<1>                        
  6 TIE                              48 p0d<0>                        
  7 wra                              49 GND                           
  8 GND                              50 TIE                           
  9 rda                              51 doe                           
 10 TIE                              52 die                           
 11 TIE                              53 kie                           
 12 a15a                             54 lcdcs                         
 13 a14a                             55 koe                           
 14 p0a<6>                           56 kint                          
 15 p0a<7>                           57 intk                          
 16 GND                              58 wrk                           
 17 p0a<5>                           59 TDO                           
 18 p0a<3>                           60 GND                           
 19 p0a<4>                           61 rdk                           
 20 p0a<2>                           62 a12k                          
 21 TIE                              63 a11k                          
 22 VCC                              64 VCC                           
 23 TIE                              65 a13k                          
 24 p0a<1>                           66 a15k                          
 25 TIE                              67 a14k                          
 26 p0a<0>                           68 p0k<0>                        
 27 GND                              69 TIE                           
 28 TDI                              70 p0k<2>                        
 29 TMS                              71 p0k<1>                        
 30 TCK                              72 p0k<3>                        
 31 TIE                              73 VCC                           
 32 intd                             74 p0k<5>                        
 33 TIE                              75 p0k<6>                        
 34 wrd                              76 p0k<4>                        
 35 rdd                              77 p0k<7>                        
 36 a13d                             78 VCC                           
 37 a14d                             79 TIE                           
 38 VCC                              80 TIE                           
 39 a15d                             81 TIE                           
 40 p0d<7>                           82 TIE                           
 41 p0d<6>                           83 TIE                           
 42 GND                              84 TIE                           


Legend :  NC  = Not Connected, unbonded pin
         PGND = Unused I/O configured as additional Ground pin
         TIE  = Unused I/O floating -- must tie to VCC, GND or other signal
         VCC  = Dedicated Power Pin
         GND  = Dedicated Ground Pin
         TDI  = Test Data In, JTAG pin
         TDO  = Test Data Out, JTAG pin
         TCK  = Test Clock, JTAG pin
         TMS  = Test Mode Select, JTAG pin
  PROHIBITED  = User reserved pin
****************************  Compiler Options  ****************************

Following is a list of all global compiler options used by the fitter run.

Device(s) Specified                         : xc95108-7-PC84
Optimization Method                         : SPEED
Multi-Level Logic Optimization              : ON
Ignore Timing Specifications                : OFF
Default Register Power Up Value             : LOW
Keep User Location Constraints              : ON
What-You-See-Is-What-You-Get                : OFF
Exhaustive Fitting                          : OFF
Keep Unused Inputs                          : OFF
Slew Rate                                   : FAST
Power Mode                                  : STD
Ground on Unused IOs                        : OFF
Global Clock Optimization                   : ON
Global Set/Reset Optimization               : ON
Global Ouput Enable Optimization            : ON
FASTConnect/UIM optimzation                 : ON
Local Feedback                              : ON
Pin Feedback                                : ON
Input Limit                                 : 36
Pterm Limit                                 : 25

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