📄 xc.rpt
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cpldfit: version I.31 Xilinx Inc.
Fitter Report
Design Name: xc Date: 4-10-2007, 2:52PM
Device Used: XC95108-7-PC84
Fitting Status: Successful
************************* Mapped Resource Summary **************************
Macrocells Product Terms Function Block Registers Pins
Used/Tot Used/Tot Inps Used/Tot Used/Tot Used/Tot
83 /108 ( 77%) 247 /540 ( 46%) 169/216 ( 78%) 58 /108 ( 54%) 49 /69 ( 71%)
** Function Block Resources **
Function Mcells FB Inps Signals Pterms IO
Block Used/Tot Used/Tot Used Used/Tot Used/Tot
FB1 10/18 14/36 14 18/90 0/12
FB2 12/18 32/36 32 42/90 6/12
FB3 16/18 29/36 29 56/90 8/12
FB4 16/18 31/36 31 49/90 3/11
FB5 13/18 32/36 32 41/90 5/11
FB6 16/18 31/36 31 41/90 10/11
----- ----- ----- -----
83/108 169/216 247/540 32/69
* - Resource is exhausted
** Global Control Resources **
Global clock net(s) unused.
Global output enable net(s) unused.
Global set/reset net(s) unused.
** Pin Resources **
Signal Type Required Mapped | Pin Type Used Total
------------------------------------|------------------------------------
Input : 17 17 | I/O : 44 63
Output : 8 8 | GCK/IO : 2 3
Bidirectional : 24 24 | GTS/IO : 2 2
GCK : 0 0 | GSR/IO : 1 1
GTS : 0 0 |
GSR : 0 0 |
---- ----
Total 49 49
** Power Data **
There are 83 macrocells in high performance mode (MCHP).
There are 0 macrocells in low power mode (MCLP).
End of Mapped Resource Summary
************************** Errors and Warnings ***************************
WARNING:Cpld:936 - The output buffer 'inta_OBUF' is missing an input and will be
deleted.
WARNING:Cpld:1007 - Removing unused input(s) 'a13a'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'aint'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'comrst'. The input(s) are unused
after optimization. Please verify functionality via simulation.
WARNING:Cpld:1007 - Removing unused input(s) 'dint'. The input(s) are unused
after optimization. Please verify functionality via simulation.
************************* Summary of Mapped Logic ************************
** 32 Outputs **
Signal Total Total Loc Pin Pin Pin Pwr Slew Reg Init
Name Pts Inps No. Type Use Mode Rate State
p0k<1> 4 8 FB2_2 71 I/O I/O STD FAST
p0k<3> 4 8 FB2_3 72 I/O I/O STD FAST
p0k<5> 4 8 FB2_5 74 GSR/I/O I/O STD FAST
p0k<6> 4 8 FB2_6 75 I/O I/O STD FAST
p0k<4> 4 8 FB2_8 76 GTS/I/O I/O STD FAST
p0k<7> 4 8 FB2_9 77 GTS/I/O I/O STD FAST
p0a<6> 4 7 FB3_2 14 I/O I/O STD FAST RESET
p0a<7> 4 7 FB3_3 15 I/O I/O STD FAST RESET
p0a<5> 4 7 FB3_5 17 I/O I/O STD FAST RESET
p0a<3> 4 7 FB3_6 18 I/O I/O STD FAST RESET
p0a<4> 4 7 FB3_8 19 I/O I/O STD FAST RESET
p0a<2> 4 7 FB3_9 20 I/O I/O STD FAST RESET
p0a<1> 4 7 FB3_14 24 I/O I/O STD FAST RESET
p0a<0> 4 7 FB3_16 26 I/O I/O STD FAST RESET
intk 2 2 FB4_2 57 I/O O STD FAST RESET
p0k<0> 4 8 FB4_14 68 I/O I/O STD FAST
p0k<2> 4 8 FB4_17 70 I/O I/O STD FAST
intd 3 4 FB5_2 32 I/O O STD FAST RESET
p0d<7> 4 7 FB5_12 40 I/O I/O STD FAST
p0d<6> 4 7 FB5_14 41 I/O I/O STD FAST
p0d<5> 4 7 FB5_15 43 I/O I/O STD FAST
p0d<4> 4 7 FB5_17 44 I/O I/O STD FAST
p0d<3> 4 7 FB6_2 45 I/O I/O STD FAST
p0d<2> 4 7 FB6_3 46 I/O I/O STD FAST
p0d<1> 4 7 FB6_5 47 I/O I/O STD FAST
p0d<0> 4 7 FB6_6 48 I/O I/O STD FAST
doe 1 2 FB6_9 51 I/O O STD FAST
die 1 2 FB6_11 52 I/O O STD FAST
kie 1 4 FB6_12 53 I/O O STD FAST
lcdcs 2 5 FB6_14 54 I/O O STD FAST
koe 1 4 FB6_15 55 I/O O STD FAST
kint 1 1 FB6_17 56 I/O O STD FAST
** 51 Buried Nodes **
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
kwrdatdo<7>/kwrdatdo<7>_CLKF__$INT 1 3 FB1_9 STD
intk_OBUF/intk_OBUF_CLKF__$INT 1 2 FB1_10 STD
dwrdat<7> 2 2 FB1_11 STD RESET
dwrdat<6> 2 2 FB1_12 STD RESET
dwrdat<5> 2 2 FB1_13 STD RESET
dwrdat<4> 2 2 FB1_14 STD RESET
dwrdat<3> 2 2 FB1_15 STD RESET
dwrdat<2> 2 2 FB1_16 STD RESET
dwrdat<1> 2 2 FB1_17 STD RESET
dwrdat<0> 2 2 FB1_18 STD RESET
kwrdatdo<1> 3 5 FB2_13 STD RESET
kwrdatdo<0> 3 5 FB2_14 STD RESET
kwrdatdl<1> 3 5 FB2_15 STD RESET
kwrdatdl<0> 3 5 FB2_16 STD RESET
kwrdatdh<1> 3 5 FB2_17 STD RESET
kwrdatdh<0> 3 5 FB2_18 STD RESET
kwrdatdo<3> 3 5 FB3_7 STD RESET
kwrdatdl<7> 3 5 FB3_10 STD RESET
kwrdatdl<6> 3 5 FB3_11 STD RESET
kwrdatdl<4> 3 5 FB3_12 STD RESET
kwrdatdl<3> 3 5 FB3_13 STD RESET
kwrdatdh<7> 3 5 FB3_15 STD RESET
kwrdatdh<6> 3 5 FB3_17 STD RESET
kwrdatdh<4> 3 5 FB3_18 STD RESET
awrdatl<7> 3 4 FB4_4 STD RESET
awrdatl<6> 3 4 FB4_5 STD RESET
awrdatl<5> 3 4 FB4_6 STD RESET
awrdatl<4> 3 4 FB4_7 STD RESET
awrdatl<3> 3 4 FB4_8 STD RESET
awrdatl<2> 3 4 FB4_9 STD RESET
awrdatl<1> 3 4 FB4_10 STD RESET
awrdath<7> 3 4 FB4_11 STD RESET
awrdath<6> 3 4 FB4_12 STD RESET
awrdath<5> 3 4 FB4_13 STD RESET
awrdath<4> 3 4 FB4_15 STD RESET
awrdath<3> 3 4 FB4_16 STD RESET
awrdath<2> 3 4 FB4_18 STD RESET
dwrdat<7>/dwrdat<7>_CLKF__$INT 1 2 FB5_7 STD
kwrdatdo<7> 3 5 FB5_8 STD RESET
kwrdatdo<6> 3 5 FB5_9 STD RESET
Signal Total Total Loc Pwr Reg Init
Name Pts Inps Mode State
kwrdatdo<5> 3 5 FB5_10 STD RESET
kwrdatdo<4> 3 5 FB5_11 STD RESET
awrdatl<0> 3 4 FB5_13 STD RESET
awrdath<1> 3 4 FB5_16 STD RESET
awrdath<0> 3 4 FB5_18 STD RESET
kwrdatdo<2> 3 5 FB6_7 STD RESET
kwrdatdl<5> 3 5 FB6_8 STD RESET
kwrdatdl<2> 3 5 FB6_10 STD RESET
kwrdatdh<5> 3 5 FB6_13 STD RESET
kwrdatdh<3> 3 5 FB6_16 STD RESET
kwrdatdh<2> 3 5 FB6_18 STD RESET
** 17 Inputs **
Signal Loc Pin Pin Pin
Name No. Type Use
ckey FB1_2 1 I/O I
wra FB1_11 7 I/O I
rda FB1_12 9 GCK/I/O I
a15a FB1_16 12 GCK/I/O I
a14a FB1_17 13 I/O I
wrk FB4_3 58 I/O I
rdk FB4_5 61 I/O I
a12k FB4_6 62 I/O I
a11k FB4_8 63 I/O I
a13k FB4_9 65 I/O I
a15k FB4_11 66 I/O I
a14k FB4_12 67 I/O I
wrd FB5_5 34 I/O I
rdd FB5_6 35 I/O I
a13d FB5_8 36 I/O I
a14d FB5_9 37 I/O I
a15d FB5_11 39 I/O I
Legend:
Pin No. - ~ - User Assigned
************************** Function Block Details ************************
Legend:
Total Pt - Total product terms used by the macrocell signal
Imp Pt - Product terms imported from other macrocells
Exp Pt - Product terms exported to other macrocells
in direction shown
Unused Pt - Unused local product terms remaining in macrocell
Loc - Location where logic was mapped in device
Pin Type/Use - I - Input GCK - Global Clock
O - Output GTS - Global Output Enable
(b) - Buried macrocell GSR - Global Set/Reset
X(@) - Signal used as input (wire-AND input) to the macrocell logic.
The number of Signals Used may exceed the number of FB Inputs
Used due to wire-ANDing in the switch matrix.
Pin No. - ~ - User Assigned
*********************************** FB1 ***********************************
Number of function block inputs used/remaining: 14/22
Number of signals used by logic mapping into function block: 14
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB1_1 (b)
(unused) 0 0 0 5 FB1_2 1 I/O I
(unused) 0 0 0 5 FB1_3 2 I/O
(unused) 0 0 0 5 FB1_4 (b)
(unused) 0 0 0 5 FB1_5 3 I/O
(unused) 0 0 0 5 FB1_6 4 I/O
(unused) 0 0 0 5 FB1_7 (b)
(unused) 0 0 0 5 FB1_8 5 I/O
kwrdatdo<7>/kwrdatdo<7>_CLKF__$INT
1 0 0 4 FB1_9 6 I/O (b)
intk_OBUF/intk_OBUF_CLKF__$INT
1 0 0 4 FB1_10 (b) (b)
dwrdat<7> 2 0 0 3 FB1_11 7 I/O I
dwrdat<6> 2 0 0 3 FB1_12 9 GCK/I/O I
dwrdat<5> 2 0 0 3 FB1_13 (b) (b)
dwrdat<4> 2 0 0 3 FB1_14 10 GCK/I/O (b)
dwrdat<3> 2 0 0 3 FB1_15 11 I/O (b)
dwrdat<2> 2 0 0 3 FB1_16 12 GCK/I/O I
dwrdat<1> 2 0 0 3 FB1_17 13 I/O I
dwrdat<0> 2 0 0 3 FB1_18 (b) (b)
Signals Used by Logic in Function Block
1: p0d<5>.PIN 6: p0d<0>.PIN 11: a15k
2: p0d<4>.PIN 7: p0d<7>.PIN 12: dwrdat<7>/dwrdat<7>_CLKF__$INT
3: p0d<3>.PIN 8: p0d<6>.PIN 13: wra
4: p0d<2>.PIN 9: a14k 14: wrk
5: p0d<1>.PIN 10: a15a
Signal 1 2 3 4 Signals FB
Name 0----+----0----+----0----+----0----+----0 Used Inputs
kwrdatdo<7>/kwrdatdo<7>_CLKF__$INT
........X.X..X.......................... 3 3
intk_OBUF/intk_OBUF_CLKF__$INT
.........X..X........................... 2 2
dwrdat<7> ......X....X............................ 2 2
dwrdat<6> .......X...X............................ 2 2
dwrdat<5> X..........X............................ 2 2
dwrdat<4> .X.........X............................ 2 2
dwrdat<3> ..X........X............................ 2 2
dwrdat<2> ...X.......X............................ 2 2
dwrdat<1> ....X......X............................ 2 2
dwrdat<0> .....X.....X............................ 2 2
0----+----1----+----2----+----3----+----4
0 0 0 0
*********************************** FB2 ***********************************
Number of function block inputs used/remaining: 32/4
Number of signals used by logic mapping into function block: 32
Signal Total Imp Exp Unused Loc Pin Pin Pin
Name Pt Pt Pt Pt # Type Use
(unused) 0 0 0 5 FB2_1 (b)
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