xc.vhd

基于CPLD XC95018开发的一段VHDL代码

LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
ENTITY xc IS
	PORT(
		
--EXTERNAL INTERFACE
	--KEY AND LCD
		p0k		: INOUT	STD_LOGIC_VECTOR(7 DOWNTO 0);
		
		a11k		: IN		STD_LOGIC;
		a12k		: IN		STD_LOGIC;
		a13k		: IN		STD_LOGIC;
		a14k		: IN		STD_LOGIC;
		a15k		: IN		STD_LOGIC;
		
		rdk		: IN		STD_LOGIC;
		wrk		: IN		STD_LOGIC;

		lcdcs		: OUT		STD_LOGIC;
		kie		: OUT		STD_LOGIC;
		koe		: OUT		STD_LOGIC;
		kint		: OUT		STD_LOGIC;
		intk		: OUT		STD_LOGIC;

	--AD
		p0a		: INOUT	STD_LOGIC_VECTOR(7 DOWNTO 0);

		a13a		: IN		STD_LOGIC;
		a14a		: IN		STD_LOGIC;
		a15a		: IN		STD_LOGIC;
		
		rda		: IN		STD_LOGIC;
		wra		: IN		STD_LOGIC;

		aint		: IN		STD_LOGIC;
		inta		: OUT		STD_LOGIC;

	--DA
		p0d		: INOUT	STD_LOGIC_VECTOR(7 DOWNTO 0);

		a13d		: IN		STD_LOGIC;
		a14d		: IN		STD_LOGIC;
		a15d		: IN		STD_LOGIC;
		
		rdd		: IN		STD_LOGIC;
		wrd		: IN		STD_LOGIC;

		dint		: IN		STD_LOGIC;
		intd		: OUT		STD_LOGIC;

		die		: OUT		STD_LOGIC;
		doe		: OUT		STD_LOGIC;
		
--RESET
		comrst	: IN		STD_LOGIC;
		ckey		: IN		STD_LOGIC
		);
END xc;

ARCHITECTURE behav OF xc IS

--INTERNAL INTERFACE
----------------------------------------------------------
--KEY AND LCD
----------------------------------------------------------
--mux
	SIGNAL krddat		: STD_LOGIC_VECTOR(7 DOWNTO 0);
	SIGNAL kxaddress	: STD_LOGIC_VECTOR(1 downto 0);

--internal registers
	SIGNAL ekwr			: STD_LOGIC;

	SIGNAL kwrdatdl	: STD_LOGIC_VECTOR(7 downto 0);
	SIGNAL kwrdatdh	: STD_LOGIC_VECTOR(7 downto 0);
	SIGNAL kwrdatdo	: STD_LOGIC_VECTOR(7 downto 0);---0913
	
	SIGNAL kwrdata		: STD_LOGIC_VECTOR(7 downto 0);

----------------------------------------------------------
--AD
----------------------------------------------------------
	--internal registers
	SIGNAL awrdath		: STD_LOGIC_VECTOR(7 downto 0);
	SIGNAL awrdatl		: STD_LOGIC_VECTOR(7 downto 0);
	SIGNAL eawr			: STD_LOGIC;

----------------------------------------------------------
--DA
----------------------------------------------------------
	SIGNAL dxaddress	: STD_LOGIC_VECTOR(1 downto 0);
	SIGNAL drddat		: STD_LOGIC_VECTOR(7 downto 0);
	SIGNAL dwrdat		: STD_LOGIC_VECTOR(7 downto 0);
	SIGNAL edwr			: STD_LOGIC;


BEGIN

---------------------------------------------------------
---------------------------------------------------------
--KEY AND LCD
---------------------------------------------------------

lcdcs	<=     (a15k AND NOT a14k AND     a13k) AND (wrk NAND rdk);
koe	<=  NOT(a15k AND NOT a14k AND NOT a13k  AND  NOT wrk);
kie	<=  NOT(a15k AND NOT a14k AND NOT a13k  AND  NOT rdk);

kint  <=  ckey;

kxaddress <= a12k & a11k;

PROCESS(kxaddress,awrdatl,awrdath,dwrdat)
BEGIN
	CASE	kxaddress IS
		WHEN "00" =>	krddat <= awrdatl;
		WHEN "01" =>	krddat <= awrdath;
		WHEN "10" =>	krddat <= dwrdat;
		WHEN "11" =>	krddat <= dwrdat;
 		WHEN OTHERS => krddat <= "XXXXXXXX";
	END CASE;
END PROCESS;

PROCESS (a14k,a15k,rdk,krddat)
BEGIN
	IF (a15k='1') AND (a14k='1') AND (rdk='0') THEN
		p0k	<= krddat;
	ELSE
		p0k	<="ZZZZZZZZ";
	END IF;
END PROCESS;

--****************************************************
ekwr <= a15k AND a14k AND NOT wrk;

PROCESS (kxaddress,p0k,ekwr)
BEGIN
	IF FALLING_EDGE(ekwr) THEN
			CASE kxaddress IS
				WHEN "00" =>	kwrdata  <= p0k;
				WHEN "01" =>	kwrdatdo <= p0k;
				WHEN "10" =>	kwrdatdl <= p0k; 	intd <= '0';
				WHEN "11" =>	kwrdatdh <= p0k; 	intd <= '1';
	 			WHEN OTHERS => NULL;
			END CASE;
		END IF;
END PROCESS;


---------------------------------------------------------
---------------------------------------------------------
--ANALOG TO DIGITAL
---------------------------------------------------------
PROCESS (rda,a15a,kwrdata)
BEGIN
	IF (a15a='1') AND (rda='0') THEN
		p0a	<=  kwrdata;
	ELSE
		p0a	<= "ZZZZZZZZ";
	END IF;
END PROCESS;

eawr <= NOT wra AND a15a;

PROCESS (eawr,a14a)
BEGIN
	IF FALLING_EDGE(eawr) THEN
		intk	<= a14a;
	
		IF (a14a='1') THEN
			awrdath <= p0a;
		ELSE
			awrdatl <= p0a;
		END IF;
	END IF;
END PROCESS;


---------------------------------------------------------
---------------------------------------------------------
--DIGITAL TO ANALOG AND DO AND DI
---------------------------------------------------------
dxaddress <= a14d & a13d;

PROCESS(dxaddress,kwrdatdl,kwrdatdh,kwrdatdo)
BEGIN
	CASE	dxaddress IS
		WHEN "00" =>	drddat <= kwrdatdo;
		WHEN "01" =>	drddat <= kwrdatdo;
		WHEN "10" =>	drddat <= kwrdatdl;
		WHEN "11" =>	drddat <= kwrdatdh;
 		WHEN OTHERS => drddat <= "XXXXXXXX";
	END CASE;
	
END PROCESS;


PROCESS (rdd,a15d,drddat)
BEGIN
	IF (a15d='1') AND (rdd='0') THEN
		p0d	<= drddat;
	ELSE
		p0d	<="ZZZZZZZZ";
	END IF;
END PROCESS;


edwr <= NOT wrd AND a15d;

PROCESS (edwr,p0d)
BEGIN
	IF FALLING_EDGE(edwr) THEN
			dwrdat <= p0d;
	END IF;
END PROCESS;


die  	 <= NOT(NOT a15d AND NOT rdd);
doe	 <= NOT(NOT a15d AND NOT wrd);

END behav;