xc.syr

基于CPLD XC95018开发的一段VHDL代码

Release  - xst I.31
Copyright (c) 1995-2006 Xilinx, Inc.  All rights reserved.
--> Parameter TMPDIR set to ./xst/projnav.tmp
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s
 
--> Parameter xsthdpdir set to ./xst
CPU : 0.00 / 0.45 s | Elapsed : 0.00 / 0.00 s
 
--> Reading design: xc.prj

TABLE OF CONTENTS
  1) Synthesis Options Summary
  2) HDL Compilation
  3) Design Hierarchy Analysis
  4) HDL Analysis
  5) HDL Synthesis
     5.1) HDL Synthesis Report
  6) Advanced HDL Synthesis
     6.1) Advanced HDL Synthesis Report
  7) Low Level Synthesis
  8) Partition Report
  9) Final Report

=========================================================================
*                      Synthesis Options Summary                        *
=========================================================================
---- Source Parameters
Input File Name                    : "xc.prj"
Input Format                       : mixed
Ignore Synthesis Constraint File   : NO

---- Target Parameters
Output File Name                   : "xc"
Output Format                      : NGC
Target Device                      : XC9500 CPLDs

---- Source Options
Top Module Name                    : xc
Automatic FSM Extraction           : YES
FSM Encoding Algorithm             : Auto
Mux Extraction                     : YES
Resource Sharing                   : YES

---- Target Options
Add IO Buffers                     : YES
MACRO Preserve                     : YES
XOR Preserve                       : YES
Equivalent register Removal        : YES

---- General Options
Optimization Goal                  : Speed
Optimization Effort                : 1
Keep Hierarchy                     : YES
RTL Output                         : Yes
Hierarchy Separator                : /
Bus Delimiter                      : <>
Case Specifier                     : maintain

---- Other Options
lso                                : xc.lso
verilog2001                        : YES
safe_implementation                : No
wysiwyg                            : NO

=========================================================================


=========================================================================
*                          HDL Compilation                              *
=========================================================================
Compiling vhdl file "F:/cpld/xc.vhd" in Library work.
Architecture behav of Entity xc is up to date.

=========================================================================
*                     Design Hierarchy Analysis                         *
=========================================================================
Analyzing hierarchy for entity <xc> in library <work> (architecture <behav>).

Building hierarchy successfully finished.

=========================================================================
*                            HDL Analysis                               *
=========================================================================
Analyzing Entity <xc> in library <work> (Architecture <behav>).
INFO:Xst:1561 - "F:/cpld/xc.vhd" line 117: Mux is complete : default of case is discarded
INFO:Xst:1561 - "F:/cpld/xc.vhd" line 189: Mux is complete : default of case is discarded
Entity <xc> analyzed. Unit <xc> generated.


=========================================================================
*                           HDL Synthesis                               *
=========================================================================

Performing bidirectional port resolution...

Synthesizing Unit <xc>.
    Related source file is "F:/cpld/xc.vhd".
WARNING:Xst:647 - Input <aint> is never used.
WARNING:Xst:647 - Input <a13a> is never used.
WARNING:Xst:647 - Input <comrst> is never used.
WARNING:Xst:1306 - Output <inta> is never assigned.
WARNING:Xst:647 - Input <dint> is never used.
    Found 8-bit tristate buffer for signal <p0k>.
    Found 1-bit register for signal <intk>.
    Found 8-bit tristate buffer for signal <p0a>.
    Found 8-bit tristate buffer for signal <p0d>.
    Found 1-bit register for signal <intd>.
    Found 8-bit register for signal <awrdath>.
    Found 8-bit register for signal <awrdatl>.
    Found 8-bit register for signal <dwrdat>.
    Found 8-bit register for signal <kwrdata>.
    Found 8-bit register for signal <kwrdatdh>.
    Found 8-bit register for signal <kwrdatdl>.
    Found 8-bit register for signal <kwrdatdo>.
    Summary:
	inferred   2 D-type flip-flop(s).
	inferred  24 Tristate(s).
Unit <xc> synthesized.


=========================================================================
HDL Synthesis Report

Macro Statistics
# Registers                                            : 9
 1-bit register                                        : 2
 8-bit register                                        : 7
# Tristates                                            : 3
 8-bit tristate buffer                                 : 3

=========================================================================

=========================================================================
*                       Advanced HDL Synthesis                          *
=========================================================================


=========================================================================
Advanced HDL Synthesis Report

Macro Statistics
# Registers                                            : 26
 Flip-Flops                                            : 26

=========================================================================

=========================================================================
*                         Low Level Synthesis                           *
=========================================================================

Optimizing unit <xc> ...

=========================================================================
*                          Partition Report                             *
=========================================================================

Partition Implementation Status
-------------------------------

  No Partitions were found in this design.

-------------------------------

=========================================================================
*                            Final Report                               *
=========================================================================
Final Results
RTL Top Level Output File Name     : xc.ngr
Top Level Output File Name         : xc
Output Format                      : NGC
Optimization Goal                  : Speed
Keep Hierarchy                     : YES
Target Technology                  : XC9500 CPLDs
Macro Preserve                     : YES
XOR Preserve                       : YES
wysiwyg                            : NO

Design Statistics
# IOs                              : 54

Cell Usage :
# BELS                             : 366
#      AND2                        : 175
#      AND4                        : 2
#      INV                         : 103
#      OR2                         : 86
# FlipFlops/Latches                : 58
#      FD                          : 58
# IO Buffers                       : 49
#      IBUF                        : 17
#      IOBUFE                      : 24
#      OBUF                        : 8
=========================================================================
CPU : 6.81 / 7.28 s | Elapsed : 7.00 / 7.00 s
 
--> 

Total memory usage is 113812 kilobytes

Number of errors   :    0 (   0 filtered)
Number of warnings :    5 (   0 filtered)
Number of infos    :    2 (   0 filtered)