📄 control.rpt
字号:
E18 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 3/22( 13%)
E19 8/ 8(100%) 3/ 8( 37%) 4/ 8( 50%) 1/2 0/2 8/22( 36%)
E21 7/ 8( 87%) 1/ 8( 12%) 1/ 8( 12%) 0/2 0/2 15/22( 68%)
E22 8/ 8(100%) 1/ 8( 12%) 2/ 8( 25%) 0/2 0/2 15/22( 68%)
E23 8/ 8(100%) 3/ 8( 37%) 5/ 8( 62%) 1/2 0/2 6/22( 27%)
F1 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 11/22( 50%)
F2 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
F3 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
F4 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 6/22( 27%)
F5 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
F6 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 4/22( 18%)
F7 6/ 8( 75%) 0/ 8( 0%) 3/ 8( 37%) 1/2 0/2 7/22( 31%)
F8 3/ 8( 37%) 0/ 8( 0%) 2/ 8( 25%) 1/2 0/2 5/22( 22%)
F9 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 0/2 9/22( 40%)
F11 2/ 8( 25%) 1/ 8( 12%) 1/ 8( 12%) 1/2 0/2 1/22( 4%)
F13 8/ 8(100%) 0/ 8( 0%) 3/ 8( 37%) 0/2 0/2 14/22( 63%)
F14 8/ 8(100%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 9/22( 40%)
F15 6/ 8( 75%) 0/ 8( 0%) 2/ 8( 25%) 0/2 0/2 14/22( 63%)
F16 1/ 8( 12%) 0/ 8( 0%) 1/ 8( 12%) 0/2 0/2 1/22( 4%)
F17 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 1/2 1/2 15/22( 68%)
F18 8/ 8(100%) 3/ 8( 37%) 8/ 8(100%) 1/2 1/2 5/22( 22%)
F19 8/ 8(100%) 4/ 8( 50%) 5/ 8( 62%) 2/2 1/2 10/22( 45%)
F20 7/ 8( 87%) 0/ 8( 0%) 6/ 8( 75%) 1/2 1/2 5/22( 22%)
F21 8/ 8(100%) 1/ 8( 12%) 5/ 8( 62%) 2/2 1/2 11/22( 50%)
F22 8/ 8(100%) 0/ 8( 0%) 7/ 8( 87%) 1/2 1/2 6/22( 27%)
F23 8/ 8(100%) 0/ 8( 0%) 4/ 8( 50%) 0/2 0/2 11/22( 50%)
F24 8/ 8(100%) 0/ 8( 0%) 5/ 8( 62%) 1/2 1/2 14/22( 63%)
Embedded Column Row
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 6/6 (100%)
Total I/O pins used: 155/183 ( 84%)
Total logic cells used: 637/1152 ( 55%)
Total embedded cells used: 0/48 ( 0%)
Total EABs used: 0/6 ( 0%)
Average fan-in: 3.13/4 ( 78%)
Total fan-in: 1999/4608 ( 43%)
Total input pins required: 52
Total input I/O cell registers required: 0
Total output pins required: 61
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 48
Total reserved pins required 0
Total logic cells required: 637
Total flipflops required: 181
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 3
Synthesized logic cells: 209/1152 ( 18%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 8 7 8 8 8 7 8 2 8 8 8 0 0 5 7 6 8 0 3 0 0 8 1 8 134/0
B: 1 1 8 2 0 2 0 0 1 0 2 0 0 8 2 1 1 1 0 1 0 8 1 3 0 43/0
C: 8 8 8 2 8 2 4 1 2 8 8 1 0 1 8 8 8 8 8 0 1 1 3 2 8 116/0
D: 7 3 2 0 0 0 1 2 1 4 0 3 0 8 8 5 8 8 7 8 8 8 7 8 8 114/0
E: 0 0 8 0 3 1 1 8 8 8 0 2 0 8 2 2 8 6 2 8 0 7 8 8 0 98/0
F: 8 1 1 8 1 8 6 3 8 0 2 0 0 8 8 6 1 8 8 8 7 8 8 8 8 132/0
Total: 32 21 34 20 20 21 19 22 22 28 20 14 0 33 33 29 32 39 25 28 16 32 35 30 32 637/0
Device-Specific Information: h:\can\cpld\rev_1\control.rpt
control
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
134 - - E -- INPUT 0 0 0 1 aen
90 - - - -- INPUT G 0 0 0 0 alea
212 - - - -- INPUT G 0 0 0 0 aleb
157 - - C -- BIDIR 0 1 0 1 iol0
141 - - E -- BIDIR 0 1 0 1 iol1
136 - - E -- BIDIR 0 1 0 1 iol2
40 - - E -- BIDIR 0 1 0 1 iol3
12 - - A -- BIDIR 0 1 0 1 iol4
41 - - E -- BIDIR 0 1 0 1 iol5
9 - - A -- BIDIR 0 1 0 1 iol6
144 - - D -- BIDIR 0 1 0 1 iol7
210 - - - -- INPUT G 0 0 0 45 ior
128 - - F -- BIDIR 0 1 0 1 iora0
49 - - F -- BIDIR 0 1 0 1 iora1
24 - - C -- BIDIR 0 1 0 1 iora2
13 - - B -- BIDIR 0 1 0 1 iora3
167 - - B -- BIDIR 0 1 0 1 iora4
20 - - B -- BIDIR 0 1 0 1 iora5
30 - - C -- BIDIR 0 1 0 1 iora6
139 - - E -- BIDIR 0 1 0 1 iora7
163 - - B -- BIDIR 0 1 0 1 iorb0
161 - - B -- BIDIR 0 1 0 1 iorb1
156 - - C -- BIDIR 0 1 0 1 iorb2
154 - - C -- BIDIR 0 1 0 1 iorb3
17 - - B -- BIDIR 0 1 0 1 iorb4
14 - - B -- BIDIR 0 1 0 1 iorb5
55 - - F -- BIDIR 0 1 0 1 iorb6
148 - - D -- BIDIR 0 1 0 1 iorb7
211 - - - -- INPUT G 0 0 0 2 iow
108 - - - 06 INPUT 0 0 0 2 jp0
107 - - - 07 INPUT 0 0 0 4 jp1
111 - - - 05 INPUT 0 0 0 3 jp2
190 - - - 04 INPUT 0 0 0 4 jp3
94 - - - 12 INPUT 0 0 0 2 jp4
191 - - - 05 INPUT 0 0 0 4 jp5
203 - - - 10 INPUT 0 0 0 3 jp6
105 - - - 08 INPUT 0 0 0 4 jp7
61 - - F -- BIDIR 0 1 0 3 p0a0
50 - - F -- BIDIR 0 1 0 3 p0a1
26 - - C -- BIDIR 0 1 0 2 p0a2
18 - - B -- BIDIR 0 1 0 2 p0a3
164 - - B -- BIDIR 0 1 0 2 p0a4
19 - - B -- BIDIR 0 1 0 2 p0a5
23 - - C -- BIDIR 0 1 0 2 p0a6
137 - - E -- BIDIR 0 1 0 2 p0a7
166 - - B -- BIDIR & 0 1 0 3 p0b0
188 - - - 04 BIDIR & 0 1 0 3 p0b1
158 - - C -- BIDIR 0 1 0 2 p0b2
159 - - C -- BIDIR 0 1 0 2 p0b3
21 - - B -- BIDIR 0 1 0 2 p0b4
15 - - B -- BIDIR 0 1 0 2 p0b5
132 - - F -- BIDIR 0 1 0 2 p0b6
147 - - D -- BIDIR 0 1 0 2 p0b7
66 - - - 22 INPUT 0 0 0 1 p2a0
231 - - - 21 INPUT 0 0 0 1 p2a1
228 - - - 20 INPUT 0 0 0 1 p2a2
75 - - - 18 INPUT 0 0 0 1 p2a3
68 - - - 21 INPUT 0 0 0 1 p2a4
236 - - - 23 INPUT 0 0 0 1 p2a5
214 - - - 14 INPUT 0 0 0 4 p2a6
79 - - - 17 INPUT 0 0 0 2 p2a7
106 - - - 07 INPUT 0 0 0 2 p2b0
39 - - D -- INPUT 0 0 0 2 p2b1
38 - - D -- INPUT 0 0 0 2 p2b2
207 - - - 12 INPUT 0 0 0 2 p2b3
35 - - D -- INPUT 0 0 0 2 p2b4
36 - - D -- INPUT 0 0 0 2 p2b5
33 - - D -- INPUT 0 0 0 2 p2b6
31 - - D -- INPUT 0 0 0 2 p2b7
223 - - - 18 INPUT 0 0 0 4 rda
195 - - - 07 INPUT 0 0 0 3 rdb
92 - - - -- INPUT G 0 0 0 0 rstdrv
142 - - E -- INPUT 0 0 0 11 sa0
118 - - - 02 INPUT 0 0 0 6 sa1
193 - - - 06 INPUT 0 0 0 6 sa2
202 - - - 10 INPUT 0 0 0 1 sa3
101 - - - 09 INPUT 0 0 0 1 sa4
138 - - E -- INPUT 0 0 0 1 sa5
117 - - - 02 INPUT 0 0 0 1 sa6
109 - - - 06 INPUT 0 0 0 1 sa7
185 - - - 02 INPUT 0 0 0 1 sa8
206 - - - 11 INPUT 0 0 0 1 sa9
103 - - - 08 INPUT 0 0 0 1 sa10
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