📄 control.srr
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$ Start of Compile
#Fri Nov 23 13:41:33 2007
Synplicity VHDL Compiler, version 7.0.0, Build 130R, built Nov 16 2001
Copyright (C) 1994-2001, Synplicity Inc. All Rights Reserved
VHDL syntax check successful!
Compiler output is up to date. No re-compile necessary
Synthesizing work.control.body_control
Post processing for work.control.body_control
@W:"H:\can\cpld\rev_1\control.vhd":367:4:367:5|Optimizing register bit wr_a_up(0) to a constant 0
@W:"H:\can\cpld\rev_1\control.vhd":425:4:425:5|Optimizing register bit wr_a_down(0) to a constant 0
@W:"H:\can\cpld\rev_1\control.vhd":492:4:492:5|Optimizing register bit wr_b_up(0) to a constant 0
@W:"H:\can\cpld\rev_1\control.vhd":548:4:548:5|Optimizing register bit wr_b_down(0) to a constant 0
@W:"H:\can\cpld\rev_1\control.vhd":356:2:356:3|Input highz to this expression [tri] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@W:"H:\can\cpld\rev_1\control.vhd":481:2:481:3|Input highz to this expression [tri] has undriven bits which are being tied to 0 - a simulation mismatch is possible
@END
Process took 0.063 seconds realtime, 0.062 seconds cputime
Synplicity Altera Technology Mapper, version 7.0.0, Build 129R, built Nov 12 2001
Copyright (C) 1994-2001, Synplicity Inc. All Rights Reserved
@N:"h:\can\cpld\rev_1\control.vhd":289:4:289:5|Found counter in view:work.control(body_control) inst bcd_b_down[3:0]
@N:"h:\can\cpld\rev_1\control.vhd":289:4:289:5|Found counter in view:work.control(body_control) inst bcd_a_down[3:0]
@N:"h:\can\cpld\rev_1\control.vhd":327:4:327:5|Found counter in view:work.control(body_control) inst bcd_b_up[3:0]
@N:"h:\can\cpld\rev_1\control.vhd":317:4:317:5|Found counter in view:work.control(body_control) inst bcd_a_up[3:0]
Writing Analyst data base E:\work\design\can\cpld\rev_1\control.srm
Writing EDIF Netlist and constraint files
Found clock alea with period 1000.00ns
Found clock aleb with period 1000.00ns
Found clock wra with period 1000.00ns
Found clock wrb with period 1000.00ns
Found clock ior with period 1000.00ns
Found clock iow with period 1000.00ns
Found clock sysclk with period 1000.00ns
Found clock mcu_command_a_inferred_clock[0] with period 1000.00ns
Found clock commandb_inferred_clock[1] with period 1000.00ns
Found clock mcu_command_b_inferred_clock[0] with period 1000.00ns
Found clock commandb_inferred_clock[0] with period 1000.00ns
Found clock mcu_command_b_inferred_clock[1] with period 1000.00ns
Found clock mcu_command_a_inferred_clock[1] with period 1000.00ns
@W:"h:\can\cpld\rev_1\control.vhd":193:1:193:2|Warning: Multiple clocks found on instance rwl; propagating only clock:iow.
@W:|Warning: Multiple clocks found on instance commandb_m[1]; propagating only clock:commandb_inferred_clock[1].
@W:|Warning: Multiple clocks found on instance commandb_m[0]; propagating only clock:commandb_inferred_clock[0].
@W:|Warning: Multiple clocks found on instance sd_iv_1_532; propagating only clock:commandb_inferred_clock[1].
@W:"h:\can\cpld\rev_1\control.vhd":540:8:540:39|Warning: Multiple clocks found on instance un97_statb; propagating only clock:mcu_command_b_inferred_clock[1].
@W:"h:\can\cpld\rev_1\control.vhd":596:8:596:44|Warning: Multiple clocks found on instance un211_statb; propagating only clock:commandb_inferred_clock[0].
@W:|Warning: Multiple clocks found on instance sd_iv_0_538; propagating only clock:commandb_inferred_clock[0].
@W:|Warning: Multiple clocks found on instance sd_iv_1_533; propagating only clock:commandb_inferred_clock[1].
@W:|Warning: Multiple clocks found on instance sd_iv_0_539; propagating only clock:commandb_inferred_clock[0].
@W:|Warning: Multiple clocks found on instance sd_iv[1]; propagating only clock:commandb_inferred_clock[1].
@W:|Warning: Multiple clocks found on instance sd_iv[0]; propagating only clock:commandb_inferred_clock[0].
@W:"h:\can\cpld\rev_1\control.vhd":245:12:245:27|Net un39_commandaa_0 appears to be a clock source which was not identified. Assuming default frequency.
@W:"h:\can\cpld\rev_1\control.vhd":243:11:243:26|Net un31_commandaa_0 appears to be a clock source which was not identified. Assuming default frequency.
##### START TIMING REPORT #####
# Timing Report written on Fri Nov 23 13:41:36 2007
#
Top view: control
Slew propagation mode: worst
Paths requested: 5
Constraint File(s):
@N| This timing report estimates place and route data. Please look at the place and route timing report for final timing.
Performance Summary
*******************
Worst slack in design: 475.100
Requested Estimated Requested Estimated Clock
Starting Clock Frequency Frequency Period Period Slack Type
----------------------------------------------------------------------------------------------------------------
alea 1.0 MHz 54.9 MHz 1000.000 18.200 981.800 inferred
aleb 1.0 MHz 65.8 MHz 1000.000 15.200 984.800 inferred
commandb_inferred_clock[0] 1.0 MHz 1.9 MHz 1000.000 520.100 479.900 inferred
commandb_inferred_clock[1] 1.0 MHz 16.1 MHz 1000.000 62.100 937.900 inferred
ior 1.0 MHz 70.9 MHz 1000.000 14.100 985.900 inferred
iow 1.0 MHz 38.3 MHz 1000.000 26.100 973.900 inferred
mcu_command_a_inferred_clock[0] 1.0 MHz 16.1 MHz 1000.000 62.100 937.900 inferred
mcu_command_a_inferred_clock[1] 1.0 MHz 1.9 MHz 1000.000 524.900 475.100 inferred
mcu_command_b_inferred_clock[0] 1.0 MHz 16.1 MHz 1000.000 62.100 937.900 inferred
mcu_command_b_inferred_clock[1] 1.0 MHz 1.9 MHz 1000.000 520.100 479.900 inferred
sysclk 1.0 MHz 2.0 MHz 1000.000 508.100 491.900 inferred
System 1.0 MHz 16.1 MHz 1000.000 62.100 937.900 system
================================================================================================================
Clock Relationships
*******************
Starting Ending r/r f/f r/f f/r
Clock Clock time (ns) time (ns) time (ns) time (ns)
---------------------------------------------------------------------------------------------------------------------------
alea alea - 1000.0 - -
aleb aleb - 1000.0 - -
ior ior 1000.0 - - -
iow iow 1000.0 - - -
iow sysclk 1000.0 - - -
sysclk sysclk 1000.0 - - -
sysclk mcu_command_a_inferred_clock[0] 1000.0 - - -
sysclk commandb_inferred_clock[1] 1000.0 - - -
sysclk mcu_command_b_inferred_clock[0] 1000.0 - - -
sysclk commandb_inferred_clock[0] - - 500.0 -
sysclk mcu_command_b_inferred_clock[1] - - 500.0 -
sysclk mcu_command_a_inferred_clock[1] - - 500.0 -
mcu_command_a_inferred_clock[0] sysclk 1000.0 - - -
mcu_command_a_inferred_clock[0] mcu_command_a_inferred_clock[0] 1000.0 - - -
commandb_inferred_clock[1] sysclk 1000.0 - - -
commandb_inferred_clock[1] commandb_inferred_clock[1] 1000.0 - - -
mcu_command_b_inferred_clock[0] sysclk 1000.0 - - -
mcu_command_b_inferred_clock[0] mcu_command_b_inferred_clock[0] 1000.0 - - -
commandb_inferred_clock[0] sysclk - - - 500.0
commandb_inferred_clock[0] commandb_inferred_clock[0] - 1000.0 - -
mcu_command_b_inferred_clock[1] sysclk - - - 500.0
mcu_command_b_inferred_clock[1] mcu_command_b_inferred_clock[1] - 1000.0 - -
mcu_command_a_inferred_clock[1] sysclk - - - 500.0
mcu_command_a_inferred_clock[1] mcu_command_a_inferred_clock[1] - 1000.0 - -
===========================================================================================================================
Interface Information
*********************
Input Ports:
Port Starting User Arrival Required
Name Reference Constraint Time Time Slack
Clock
--------------------------------------------------------------------------------
aen NA NA NA NA NA
alea NA NA NA NA NA
aleb NA NA NA NA NA
iol[0] NA NA NA NA NA
iol[1] NA NA NA NA NA
iol[2] NA NA NA NA NA
iol[3] NA NA NA NA NA
iol[4] NA NA NA NA NA
iol[5] NA NA NA NA NA
iol[6] NA NA NA NA NA
iol[7] NA NA NA NA NA
ior ior (rising) NA 0.000 991.000 991.000
iora[0] NA NA NA NA NA
iora[1] NA NA NA NA NA
iora[2] System (rising) NA 0.000 1000.000 1000.000
iora[3] System (rising) NA 0.000 1000.000 1000.000
iora[4] System (rising) NA 0.000 1000.000 1000.000
iora[5] System (rising) NA 0.000 1000.000 1000.000
iora[6] System (rising) NA 0.000 1000.000 1000.000
iora[7] System (rising) NA 0.000 1000.000 1000.000
iorb[0] NA NA NA NA NA
iorb[1] NA NA NA NA NA
iorb[2] System (rising) NA 0.000 1000.000 1000.000
iorb[3] System (rising) NA 0.000 1000.000 1000.000
iorb[4] System (rising) NA 0.000 1000.000 1000.000
iorb[5] System (rising) NA 0.000 1000.000 1000.000
iorb[6] System (rising) NA 0.000 1000.000 1000.000
iorb[7] System (rising) NA 0.000 1000.000 1000.000
iow iow (rising) NA 0.000 985.000 985.000
jp[0] NA NA NA NA NA
jp[1] NA NA NA NA NA
jp[2] NA NA NA NA NA
jp[3] NA NA NA NA NA
jp[4] NA NA NA NA NA
jp[5] NA NA NA NA NA
jp[6] NA NA NA NA NA
jp[7] NA NA NA NA NA
p0a[0] System (rising) NA 0.000 998.100 998.100
p0a[1] System (rising) NA 0.000 998.100 998.100
p0a[2] System (rising) NA 0.000 998.100 998.100
p0a[3] System (rising) NA 0.000 998.100 998.100
p0a[4] System (rising) NA 0.000 998.100 998.100
p0a[5] System (rising) NA 0.000 998.100 998.100
p0a[6] System (rising) NA 0.000 998.100 998.100
p0a[7] System (rising) NA 0.000 998.100 998.100
p0b[0] System (rising) NA 0.000 998.100 998.100
p0b[1] System (rising) NA 0.000 998.100 998.100
p0b[2] System (rising) NA 0.000 998.100 998.100
p0b[3] System (rising) NA 0.000 998.100 998.100
p0b[4] System (rising) NA 0.000 998.100 998.100
p0b[5] System (rising) NA 0.000 998.100 998.100
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