control.vhd

一个关于4路CAN卡的硬件程序,用VHDL编写

--本程序用于711所智能CAN网卡
--此程序负责控制第一、二路CAN通道
--作者：JYH
--设计开始时间：2003年8月4日
--设计完成时间：
--版本号:1.0
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity control is
port
(jp                            :  in       std_logic_vector(7 downto 0);     --跨接针
--************************************************************************   --本段定义单片机端口引脚
 p0a, p0b                      :  inout    std_logic_vector(7 downto 0);     
 p2a, p2b                      :  in       std_logic_vector(7 downto 0);
 alea, aleb                    :  in       std_logic;
 wra, wrb                      :  in       std_logic;
 rda, rdb                      :  in       std_logic;
 c51rsta, c51rstb              :  out      std_logic;
 sjarsta, sjarstb              :  out      std_logic;
--************************************************************************   --本段定义定义双口RAM引脚
 iol, iora, iorb               :  inout    std_logic_vector(7 downto 0);
 al, ara, arb                  :  out      std_logic_vector(13 downto 0);
 cela, celb, cera, cerb        :  out      std_logic;
 oela, oelb, oera, oerb        :  out      std_logic;
 rwl, rwra, rwrb               :  out      std_logic;
--************************************************************************   --本段定义ISA总线引脚
 sd                            :  inout    std_logic_vector(7 downto 0);
 sa                            :  in       std_logic_vector(19 downto 0);
 ior, iow, aen, rstdrv         :  in       std_logic;
 sysclk                        :  in       std_logic;
 coma                          :  out      std_logic_vector(3 downto 0));
end control;

architecture body_control of control is
signal base_address                                :   std_logic_vector(4 downto 0);    --基地址
signal cs_a, cs_b           :   std_logic;                                              --A通道和B通道的片选信号
signal addressa,addressb                     :   std_logic_vector(7 downto 0);          --锁存单片机地址总线低8位
signal wr_a_up, wr_b_up, wr_a_down, wr_b_down                                :  integer range 0 to 30000;   --堆栈区栈顶指针
signal rd_a_up, rd_b_up, rd_a_down, rd_b_down                                :  integer range 0 to 30000;   --堆栈区栈底指针
signal commanda,commandaa, commandb, commandbb    :  std_logic_vector(3 downto 0);  --命令字寄存器
signal stata,statb           :  std_logic_vector(4 downto 0);            --状态字寄存器
signal bcd_a_up, bcd_a_down, bcd_b_up, bcd_b_down : integer range 0 to 9;
signal mcu_command_a,mcu_command_b         : std_logic_vector(1 downto 0);
signal a_up_full,a_up_empty,a_down_full,a_down_empty  : std_logic;
signal b_up_full,b_up_empty,b_down_full,b_down_empty  : std_logic;

begin
--*************************************************************************
--本段描述单片机与双口RAM连接关系
process(p2a,alea,rda,wra)
begin
    if alea'event and alea='0' then   --地址锁存
	    addressa<=p0a;
	end if;
	oera<='0';                    --输出允许常低
	if p2a(7 downto 6)="01" then  --产生双口RAM片选信号
	    cera<='0';
	else
	    cera<='1';
	end if;
	if rda='0' then               --产生双口RAM读写信号
	    rwra<='1';
	else
	    rwra<=wra;
	end if;
end process;
process(wra)
begin
    if wra'event and wra='1' then
        if addressa&p2a="1000000000000000" then
 	        mcu_command_a<=p0a(1 downto 0);
		end if;
	end if;
end process;
process(rda,addressa,p2a,mcu_command_a)
begin
    if addressa&p2a="1000000000000000" and rda='0' then
	    p0a(1 downto 0)<=mcu_command_a;
	else 
	    p0a(1 downto 0)<="ZZ";
	end if;
end process;
process(wrb)
begin
    if wrb'event and wrb='1' then
        if addressa&p2b="1000000000000000" then
 	        mcu_command_b<=p0b(1 downto 0);
		end if;
	end if;
end process;
process(rdb,addressb,p2b,mcu_command_b)
begin
    if addressb&p2b="1000000000000000" and rdb='0' then
	    p0b(1 downto 0)<=mcu_command_b;
	else 
	    p0b(1 downto 0)<="ZZ";
	end if;
end process;
process(p2b,aleb,rdb,wrb) 
begin
    if aleb'event and aleb='0' then
	    addressb<=p0b;
	end if;
	oerb<='0';
	if p2b(7 downto 6)="01" then 
	    cerb<='0';
	else
	    cerb<='1';
	end if;
    if rdb='0' then
	    rwrb<='1';
	else
	    rwrb<=wrb;
	end if;
end process;

--ara<=p2a(5 downto 0)&addressa;
arb<=p2b(5 downto 0)&addressb;

process(wra,p2a,p0a)
variable data : std_logic_vector(7 downto 0);
begin
    if p2a(7 downto 6)="01" and wra='0' then
        data:=p0a;
	else
	    data:=(others=>'Z');
	end if;
	iora<=data;
end process;
process(rda,p2a,iora)
variable data : std_logic_vector(7 downto 0);
begin
    if p2a(7 downto 6)="01" and rda='0' then
	    data:=iora;
	else
	    data:=(others=>'Z');
	end if;
	p0a<=data;
end process;

process(wrb,p2b,p0b)
variable data : std_logic_vector(7 downto 0);
begin
    if p2b(7 downto 6)="01" and wrb='0' then
        data:=p0b;
	else
	    data:=(others=>'Z');
	end if;
	iorb<=data;
end process;
process(rdb,p2b,iorb)
variable data : std_logic_vector(7 downto 0);
begin
    if p2b(7 downto 6)="01" and rdb='0' then
	    data:=iorb;
	else
	    data:=(others=>'Z');
	end if;
	p0b<=data;
end process;
--*******************************************************************
process(jp)
begin
    case jp is
	    when "00000001" => base_address<="10000";
		when "00000010" => base_address<="10001";
		when "00000100" => base_address<="10010";
		when "00001000" => base_address<="10011";
		when "00010000" => base_address<="10100";
		when "00100000" => base_address<="10101";
		when "01000000" => base_address<="10110";
		when "10000000" => base_address<="10111";
		when others => base_address<="10000";
	end case;
end process;

process(aen,ior,iow,sa,base_address)
begin
    cs_a<='1';
	cs_b<='1';
	if aen&sa(16 downto 0)="0000000"&base_address&"00001" then
        cs_a<='0';
    end if;
	if aen&sa(16 downto 0)="0000000"&base_address&"00101" then
        cs_b<='0';
    end if;		
	oela<='0';
	oelb<='0';
	cela<=cs_a;
	celb<=cs_b;
	if ior='0'  then
	    rwl<='1';
	else
	    rwl<=iow;
	end if;
end process;
 
process(ior,cs_a,iol)
variable data    : std_logic_vector(7 downto 0);
begin
    if cs_a='0' and ior='0' then
	    data:=iol;
	else 
	    data:=(others=>'Z');
	end if;
	sd<=data;
end process;
process(iow,cs_a,sd)
variable data    : std_logic_vector(7 downto 0);
begin
    if cs_a='0' and iow='0' then
	    data:=sd;
	else
	    data:=(others=>'Z');
	end if;
	iol<=data;
end process;

process(ior,aen,sa,base_address,commanda)
begin
    if aen&sa(16 downto 0)="0000000"&base_address&"00000" and ior='0' then
	    sd(3 downto 0)<=commanda;
	else
        sd(3 downto 0)<=(others=>'Z');
	end if;
end process;
process(iow)
begin
    if iow'event and iow='1' then
	    if aen&sa(16 downto 0)="0000000"&base_address&"00000" then
	   		commandaa<=sd(3 downto 0);
		end if;
	end if;
end process;
process(commandaa)
begin
    if commandaa(3)='1' then
	   commanda<="1000";
	   elsif commandaa(2)='1' then
	       commanda<="0100";
		   elsif commandaa(1)='1' then
		       commanda<="0010";
			   elsif commandaa(0)='1'then
			       commanda<="0001";
			   else
			       commanda<="0000";
    end if;
end process;

process(ior,aen,sa,base_address,commandb)
begin
    if aen&sa(16 downto 0)="0000000"&base_address&"00100" and ior='0' then
	    sd(3 downto 0)<=commandb;
	else
        sd<=(others=>'Z');
	end if;
end process;
process(iow)
begin
    if iow'event and iow='1' then
	    if aen&sa(16 downto 0)="0000000"&base_address&"00100" then
	        commandbb<=sd(3 downto 0);
		end if;
	end if;
end process;
process(sysclk,commandbb)
begin
    if sysclk'event and sysclk='1' then
    if commandbb(3)='1' then
	   commandb<="1000";
	   elsif commandbb(2)='1' then
	       commandb<="0100";
		   elsif commandbb(1)='1' then
		       commandb<="0010";
			   elsif commandbb(0)='1'then
			       commandb<="0001";
			   else
			       commandb<="0000";
    end if;
	end if;
end process;
--************************************************************************************************


process(iow)
begin
    if iow'event and iow='1' then
	    if aen&sa(16 downto 0)="0000000"&base_address&"00011" then
			bcd_a_down<=conv_integer(sd(3 downto 0));
--			bcd_a_up<=conv_integer(sd(7 downto 4));
		end if;	
		if aen&sa(16 downto 0)="0000000"&base_address&"00111" then
			bcd_b_down<=conv_integer(sd(3 downto 0));
--			bcd_b_up<=conv_integer(sd(7 downto 4));
		end if;
		if commanda(0)='0' then 
            bcd_a_down<=0;
		else
		    if aen&sa(16 downto 0)="0000000"&base_address&"00001" and commanda(0)='1' then
		        bcd_a_down<=bcd_a_down+1;
		    end if;
		end if;
		if commandb(0)='0' then 
            bcd_b_down<=0;
		else
		    if aen&sa(16 downto 0)="0000000"&base_address&"00101" and commandb(0)='1' then
		        bcd_b_down<=bcd_b_down+1;
		    end if;
		end if;
	end if;
end process;
process(ior,commanda)
begin