control.sat

来自「一个关于4路CAN卡的硬件程序,用VHDL编写」· SAT 代码 · 共 11 行

define_design_name {control}
define_synthesis -family MAX7000
define_clock {|sysclk} -period 1000.000
define_clock {|iow} -period 1000.000
define_clock {|ior} -period 1000.000
define_clock {|wrb} -period 1000.000
define_clock {|wra} -period 1000.000
define_clock {|aleb} -period 1000.000
define_clock {|alea} -period 1000.000
log_puts {All Constraints processed!}