control.edf

一个关于4路CAN卡的硬件程序,用VHDL编写

           (port DATAB14 (direction INPUT))
           (port AEB (direction OUTPUT))
           (property LPM_TYPE (string "LPM_COMPARE"))
           (property WIDTH (integer 15))
           (property LPM_WIDTH (integer 15))
           (property REPRESENTATION (string "UNSIGNED"))
           (property LPM_REPRESENTATION (string "UNSIGNED"))
         )
       )
    )
    (cell SYNLPM_ADD12 (cellType GENERIC)
       (view LPM (viewType NETLIST)
         (interface
           (port DATAA0 (direction INPUT))
           (port DATAA1 (direction INPUT))
           (port DATAA2 (direction INPUT))
           (port DATAA3 (direction INPUT))
           (port DATAA4 (direction INPUT))
           (port DATAA5 (direction INPUT))
           (port DATAA6 (direction INPUT))
           (port DATAA7 (direction INPUT))
           (port DATAA8 (direction INPUT))
           (port DATAA9 (direction INPUT))
           (port DATAA10 (direction INPUT))
           (port DATAA11 (direction INPUT))
           (port DATAB0 (direction INPUT))
           (port DATAB1 (direction INPUT))
           (port DATAB2 (direction INPUT))
           (port DATAB3 (direction INPUT))
           (port DATAB4 (direction INPUT))
           (port DATAB5 (direction INPUT))
           (port DATAB6 (direction INPUT))
           (port DATAB7 (direction INPUT))
           (port DATAB8 (direction INPUT))
           (port DATAB9 (direction INPUT))
           (port DATAB10 (direction INPUT))
           (port DATAB11 (direction INPUT))
           (port RESULT0 (direction OUTPUT))
           (port RESULT1 (direction OUTPUT))
           (port RESULT2 (direction OUTPUT))
           (port RESULT3 (direction OUTPUT))
           (port RESULT4 (direction OUTPUT))
           (port RESULT5 (direction OUTPUT))
           (port RESULT6 (direction OUTPUT))
           (port RESULT7 (direction OUTPUT))
           (port RESULT8 (direction OUTPUT))
           (port RESULT9 (direction OUTPUT))
           (port RESULT10 (direction OUTPUT))
           (port RESULT11 (direction OUTPUT))
           (property LPM_TYPE (string "LPM_ADD_SUB"))
           (property WIDTH (integer 12))
           (property LPM_WIDTH (integer 12))
           (property REPRESENTATION (string "UNSIGNED"))
           (property LPM_REPRESENTATION (string "UNSIGNED"))
         )
       )
    )
  )
  (library ALTERA_MAX
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell S_DFFE (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port CLK (direction INPUT))
           (port CLRN (direction INPUT))
           (port PRN (direction INPUT))
           (port ENA (direction INPUT))
           (port Q (direction OUTPUT))
           (property is_ff (integer 1))
         )
        (property is_ff (integer 1))
       )
    )
    (cell S_DFF (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port D (direction INPUT))
           (port CLK (direction INPUT))
           (port CLRN (direction INPUT))
           (port PRN (direction INPUT))
           (port Q (direction OUTPUT))
           (property is_ff (integer 1))
         )
        (property is_ff (integer 1))
       )
    )
    (cell SOFT (cellType GENERIC)
       (view PRIM (viewType NETLIST)
         (interface
           (port A_IN (direction INPUT))
           (port A_OUT (direction OUTPUT))
         )
       )
    )
  )
  (library PrimLib
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell inv1 (cellType GENERIC)
      (view prim (viewType NETLIST)
        (interface
         (port OUT0 (direction OUTPUT))
         (port I0 (direction INPUT))
        )
      )
    )
    (cell tri1 (cellType GENERIC)
      (view prim (viewType NETLIST)
        (interface
         (port OUT0 (direction OUTPUT))
         (port I0 (direction INPUT))
         (port E (direction INPUT))
        )
      )
    )
    (cell and2 (cellType GENERIC)
      (view prim (viewType NETLIST)
        (interface
         (port OUT (direction OUTPUT))
         (port I0 (direction INPUT))
         (port I1 (direction INPUT))
        )
      )
    )
    (cell or2 (cellType GENERIC)
      (view prim (viewType NETLIST)
        (interface
         (port OUT (direction OUTPUT))
         (port I0 (direction INPUT))
         (port I1 (direction INPUT))
        )
      )
    )
    (cell xor2 (cellType GENERIC)
      (view prim (viewType NETLIST)
        (interface
         (port OUT (direction OUTPUT))
         (port I0 (direction INPUT))
         (port I1 (direction INPUT))
        )
      )
    )
    (cell mux1 (cellType GENERIC)
      (view prim (viewType NETLIST)
        (interface
         (port OUT0 (direction OUTPUT))
         (port A0 (direction INPUT))
         (port B0 (direction INPUT))
         (port SEL (direction INPUT))
        )
      )
    )
  )
  (library work
    (edifLevel 0)
    (technology (numberDefinition ))
    (cell control (cellType GENERIC)
       (view body_control (viewType NETLIST)
         (interface
           (port (array (rename jp "jp(7:0)") 8) (direction INPUT))
           (port (array (rename p0a "p0a(7:0)") 8) (direction INOUT))
           (port (array (rename p0b "p0b(7:0)") 8) (direction INOUT))
           (port (array (rename p2a "p2a(7:0)") 8) (direction INPUT))
           (port (array (rename p2b "p2b(7:0)") 8) (direction INPUT))
           (port (array (rename iol "iol(7:0)") 8) (direction INOUT))
           (port (array (rename iora "iora(7:0)") 8) (direction INOUT))
           (port (array (rename iorb "iorb(7:0)") 8) (direction INOUT))
           (port (array (rename al "al(13:0)") 14) (direction OUTPUT))
           (port (array (rename ara "ara(13:0)") 14) (direction OUTPUT))
           (port (array (rename arb "arb(13:0)") 14) (direction OUTPUT))
           (port (array (rename sd "sd(7:0)") 8) (direction INOUT))
           (port (array (rename sa "sa(19:0)") 20) (direction INPUT))
           (port (array (rename coma "coma(3:0)") 4) (direction OUTPUT))
           (port alea (direction INPUT))
           (port aleb (direction INPUT))
           (port wra (direction INPUT))
           (port wrb (direction INPUT))
           (port rda (direction INPUT))
           (port rdb (direction INPUT))
           (port ior (direction INPUT))
           (port iow (direction INPUT))
           (port aen (direction INPUT))
           (port rstdrv (direction INPUT))
           (port sysclk (direction INPUT))
           (port c51rsta (direction OUTPUT))
           (port c51rstb (direction OUTPUT))