proj_1.prj

一个关于4路CAN卡的硬件程序,用VHDL编写

#-- Synplicity, Inc.
#-- Version 7.0.2A  
#-- Project file H:\can\cpld\proj_1.prj
#-- Written on Wed Aug 28 16:49:43 2013


#add_file options
add_file -vhdl -lib work "rev_1/control.vhd"

#reporting options


#implementation: "rev_1"
impl -add rev_1

#device options
set_option -technology MAX7000
set_option -part EPM7256S

#compilation/mapping options
set_option -default_enum_encoding sequential
set_option -symbolic_fsm_compiler 1
set_option -resource_sharing 1

#map options
set_option -frequency 0.000
set_option -fanin_limit 40
set_option -domap 0
set_option -soft_buffers 1
set_option -area_delay_percent 0

#simulation options
set_option -write_verilog 0
set_option -write_vhdl 0

#automatic place and route (vendor) options
set_option -write_apr_constraint 1

#set result format/file last
project -result_file "rev_1/control.edf"
impl -active "rev_1"