disasm_raw.v

使用CPLD仿真一个80383的CPU

32'b1111011?11100???????????????????: /* MUL 2 AL,AX,EAX with reg */
32'b1111011????100??????????????????: /* MUL AL,AX,EAX with mem */
32'b1111011?11011???????????????????: /* NEG 2 reg */
32'b1111011????011??????????????????: /* NEG 2 mem */
32'b10010000????????????????????????: /* NOP 1 */
32'b000011110001111111000???????????: /* NOP 3 reg */
32'b0000111100011111???000??????????: /* NOP 3 mem */
32'b1111011?11010???????????????????: /* NOT 2 reg */
32'b1111011????010??????????????????: /* NOT 2 mem */
32'b0000100?11??????????????????????: /* OR 2 reg1 to reg2 */
32'b0000101?11??????????????????????: /* OR 2 reg2 to reg1 */
32'b0000101?????????????????????????: /* OR 2 mem to reg */
32'b0000100?????????????????????????: /* OR 2 reg to mem */
32'b100000??11001???????????????????: /* OR 3 immediate to reg */
32'b0000110?????????????????????????: /* OR 2 immediate to AL,AX,EAX */
32'b100000?????001??????????????????: /* OR 3 immediate to mem */
32'b1110011?????????????????????????: /* OUT 2 fixed port */
32'b1110111?????????????????????????: /* OUT 1 varable port */
32'b0110111?????????????????????????: /* OUTS 1 */
32'b1000111111000???????????????????: /* POP 2 reg */
32'b01011???????????????????????????: /* POP 1 reg */
32'b10001111???000??????????????????: /* POP 2 mem */
32'b000??111????????????????????????: /* POP 1 segment reg DS,ES */
32'b000??111????????????????????????: /* POP 1 segment reg SS */
32'b0000111110???001????????????????: /* POP 2 segment reg FS,GS */
32'b01100001????????????????????????: /* POPA 1 */
32'b10011101????????????????????????: /* POPF 1 */
32'b1111111111110???????????????????: /* PUSH 2 reg */
32'b01010???????????????????????????: /* PUSH 1 reg */
32'b11111111???110??????????????????: /* PUSH 2 mem */
32'b011010?0????????????????????????: /* PUSH 2 immediate */
32'b000??110????????????????????????: /* PUSH 1 segment reg CS,DS,ES,SS */
32'b0000111110???000????????????????: /* PUSH 2 segment reg FS,GS */
32'b01100000????????????????????????: /* PUSHA 1 */
32'b10011100????????????????????????: /* PUSHF 1 */
32'b1101000?11010???????????????????: /* RCL 2 reg by 1 */
32'b1101000????010??????????????????: /* RCL 2 mem by 1 */
32'b1101001?11010???????????????????: /* RCL 2 reg by CL */
32'b1101001????010??????????????????: /* RCL 2 mem by CL */
32'b1100000?11010???????????????????: /* RCL 3 reg by immediate */
32'b1100000???010???????????????????: /* RCL 3 mem by immediate */
32'b1101000?11011???????????????????: /* RCR 2 reg by 1 */
32'b1101000????011??????????????????: /* RCR 2 mem by 1 */
32'b1101001?11011???????????????????: /* RCR 2 reg by CL */
32'b1101001????011??????????????????: /* RCR 2 mem by CL */
32'b1100000?11011???????????????????: /* RCR 3 reg by immediate */
32'b1100000????011??????????????????: /* RCR 3 mem by immediate */
32'b0000111100110010????????????????: /* RDMSR 2 */
32'b0000111100110011????????????????: /* RDPMC 2 */
32'b0000111100110001????????????????: /* RDTSC 2 */
32'b111100110110110?????????????????: /* REP INS 2 */
32'b111100111010110?????????????????: /* REP LODS 2 */
32'b111100111010010?????????????????: /* REP MOVS 2 */
32'b111100110110111?????????????????: /* REP OUTS 2 */
32'b111100111010101?????????????????: /* REP STOS 2 */
32'b111100111010011?????????????????: /* REP CMPS 2 */
32'b111100111010111?????????????????: /* REPE SCAS 2 */
32'b111100101010011?????????????????: /* REPNE CMPS 2 */
32'b111100101010111?????????????????: /* REPNE SCAS 2 */
32'b11000011????????????????????????: /* RET 1 */
32'b11000010????????????????????????: /* RET 2 adding immediate to SP */
32'b11001011????????????????????????: /* RET 1 */
32'b11001010????????????????????????: /* RET 2 */
32'b1101000?11000???????????????????: /* ROL 2 reg by 1 */
32'b1101000????000??????????????????: /* ROL 2 mem by 1 */
32'b1101001?11000???????????????????: /* ROL 2 reg by CL */
32'b1101001????000??????????????????: /* ROL 2 mem by CL */
32'b1100000?11000???????????????????: /* ROL 2 reg by immediate */
32'b1100000????000??????????????????: /* ROL 2 mem by immediate */
32'b1101000?11001???????????????????: /* ROR 2 reg by 1 */
32'b1101000????001??????????????????: /* ROR 2 mem by 1 */
32'b1101001?11001???????????????????: /* ROR 2 reg by CL */
32'b1101001????001??????????????????: /* ROR 2 mem cy CL */
32'b1100000?11001???????????????????: /* ROR 3 reg by immediate */
32'b1100000????001??????????????????: /* ROR 3 mem by  immediate */
32'b0000111110101010????????????????: /* RSM 2 */
32'b10011110????????????????????????: /* SAHF 1 */
32'b1101000?11111???????????????????: /* SAR 2 reg by 1 */
32'b1101000????111??????????????????: /* SAR 2 mem by 1 */
32'b1101001?11111???????????????????: /* SAR 2 reg by CL */
32'b1101001????111??????????????????: /* SAR 2 mem by CL */
32'b1100000?11111???????????????????: /* SAR 3 reg by immediate */
32'b1100000????111??????????????????: /* SAR 3 mem by immediate */
32'b0001100?11??????????????????????: /* SBB 2 reg1 to reg2 */
32'b0001101?11??????????????????????: /* SBB 2 reg2 to reg1 */
32'b0001101?????????????????????????: /* SBB 2 mem to reg */
32'b0001100?????????????????????????: /* SBB 2 reg to mem */
32'b100000??11011???????????????????: /* SBB 3 immediate to reg */
32'b0001110?????????????????????????: /* SBB 2 immediate to AL,AX,EAX */
32'b100000?????011??????????????????: /* SBB 3 immediate to mem */
32'b1010111?????????????????????????: /* SCAS 1 */
32'b000011111001????11000???????????: /* SETcc 3 reg */
32'b000011111001???????000??????????: /* SETcc 3 mem */
32'b0000111100000001???000??????????: /* SGDT 3 */
32'b1101000?11100???????????????????: /* SHL 2 reg by 1 */
32'b1101000????100??????????????????: /* SHL 2 mem by 1 */
32'b1101001?11100???????????????????: /* SHL 2 reg by CL */
32'b1101001????100??????????????????: /* SHL 2 mem by CL */
32'b1100000?1100????????????????????: /* SHL 3 reg by immediate */
32'b1100000????100??????????????????: /* SHL 3 mem by immediate */
32'b000011111010010011??????????????: /* SHLD 4 reg by immediate */
32'b0000111110100100????????????????: /* SHLD 4 mem by immediate */
32'000011111010010111???????????????: /* SHLD 3 reg by CL */
32'b0000111110100101????????????????: /* SHLD 3 mem by CL */
32'b1101000?11101???????????????????: /* SHR 2 reg by 1 */
32'b1101000????101??????????????????: /* SHR 2 mem by 1 */
32'b1101001?11101???????????????????: /* SHR 2 reg by CL */
32'b1101001????101??????????????????: /* SHR 2 mem by CL */
32'b1100000?11101???????????????????: /* SHR 3 reg by immediate */
32'b1100000????101??????????????????: /* SHR 3 mem by immediate */
32'b000011111010110011??????????????: /* SHRD 4 reg by immediate */
32'b0000111110101100????????????????: /* SHRD 4 mem by immediate */
32'b000011111010110111??????????????: /* SHRD 3 reg by CL */
32'b0000111110101101????????????????: /* SHRD 3 mem by CL */
32'b0000111100000001???001??????????: /* SIDT 3 */
32'b000011110000000011000???????????: /* SLDT 3 to reg */
32'b0000111100000000???000??????????: /* SLDT 3 to mem */
32'b000011110000000111100???????????: /* SMSW 3 to reg */
32'b0000111100000001???100??????????: /* SMSW 3 to mem */
32'b11111001????????????????????????: /* STC 1 */
32'b11111101????????????????????????: /* STD 1 */
32'b11111011????????????????????????: /* STI 1 */
32'b1010101?????????????????????????: /* STOS 1 */
32'b000011110000000011001???????????: /* STR 3 to reg */
32'b0000111100000000???001??????????: /* STR 3 to mem */
32'b0010100?11??????????????????????: /* SUB 2 reg1 to reg2 */
32'b0010101?11??????????????????????: /* SUB 2 reg2 to reg1 */
32'b0010101?????????????????????????: /* SUB 2 mem to reg */
32'b0010100?????????????????????????: /* SUB 2 reg to mem */
32'b100000??11101???????????????????: /* SUB 3 immediate to reg */
32'b0010110?????????????????????????: /* SUB 2 immediate to AL,AX,EAX */
32'b100000?????101??????????????????: /* SUB 3 immediate to mem */
32'b1000010?11??????????????????????: /* TEST 2 reg1 and reg2 */
32'b1000010?????????????????????????: /* TEST 2 mem and reg */
32'b1111011?11000???????????????????: /* TEST 3 immediate and reg */
32'b1010100?????????????????????????: /* TEST 2 immediate and AL,AX,EAX */
32'b1111011????000??????????????????: /* TEST 3 immedaite and mem */
32'b000011110000000011100???????????: /* VERRR 3 reg */
32'b0000111100000000???100??????????: /* VERRR 3 reg */
32'b000011110000000011101???????????: /* VERW 3 reg */
32'b0000111100000000???101??????????: /* VERW 3 mem */
32'b10011011????????????????????????: /* WAIT 1 */
32'b0000111100001001????????????????: /* WBINVD 2 */
32'b0000111100110000????????????????: /* WRMSR 2 */
32'b000011111100000?11??????????????: /* XADD 3 reg1,reg2 */
32'b000011111100000?????????????????: /* XADD 3 mem,reg */
32'b1000011?11??????????????????????: /* XCHG 2 reg1 with reg2 */
32'b10010???????????????????????????: /* XCHG 1 AX,EAX with reg */
32'b1000011?????????????????????????: /* XCHg 2 mem with reg */
32'b11010111????????????????????????: /* XLAT 1 */
32'b0011000?11??????????????????????: /* XOR 2 reg1 to reg2 */
32'b0011001?11??????????????????????: /* XOR 2 reg2 to reg1 */
32'b0011001?????????????????????????: /* XOR 2 mem to reg */
32'b0011000?????????????????????????: /* XOR 2 reg to mem */
32'b100000??11110???????????????????: /* XOR 3 immediate to reg */
32'b0011010?????????????????????????: /* XOR 2 immediate to AL,AX,EAX */
32'b100000?????110??????????????????: /* XOR 3 immediate to mem */




//32'b0000ffff00001011 /* UD2 */


endcase