jiaotongdeng.map.qmsg

用Verilog HDL语言编写的交通灯程序

{ "Info" "IOPT_INFERENCING_SUMMARY" "1 " "Info: Inferred 1 megafunctions from design logic" { { "Info" "IOPT_LPM_COUNTER_INFERRED" "xianshi:inst1\|count\[0\]~0 13 " "Info: Inferred lpm_counter megafunction (LPM_WIDTH=13) from the following logic: \"xianshi:inst1\|count\[0\]~0\"" {  } { { "xianshi.v" "count\[0\]~0" { Text "F:/My_design/jiaotongdeng/xianshi.v" 13 -1 0 } }  } 0 0 "Inferred lpm_counter megafunction (LPM_WIDTH=%2!d!) from the following logic: \"%1!s!\"" 0 0}  } {  } 0 0 "Inferred %1!d! megafunctions from design logic" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_counter " "Info: Found entity 1: lpm_counter" {  } { { "lpm_counter.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_counter.tdf" 233 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 lpm_add_sub " "Info: Found entity 1: lpm_add_sub" {  } { { "lpm_add_sub.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/lpm_add_sub.tdf" 100 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/addcore.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/addcore.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 addcore " "Info: Found entity 1: addcore" {  } { { "addcore.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/addcore.tdf" 73 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 a_csnbuffer " "Info: Found entity 1: a_csnbuffer" {  } { { "a_csnbuffer.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/a_csnbuffer.tdf" 10 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/look_add.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/look_add.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 look_add " "Info: Found entity 1: look_add" {  } { { "look_add.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/look_add.tdf" 27 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "c:/altera/quartus51/libraries/megafunctions/altshift.tdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file c:/altera/quartus51/libraries/megafunctions/altshift.tdf" { { "Info" "ISGN_ENTITY_NAME" "1 altshift " "Info: Found entity 1: altshift" {  } { { "altshift.tdf" "" { Text "c:/altera/quartus51/libraries/megafunctions/altshift.tdf" 28 1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "IOPT_SMP_MACHINE_PREPROCESS_STAT_NO_BITS" "\|dingceng\|jiaotongdeng:inst\|current_state 8 " "Info: State machine \"\|dingceng\|jiaotongdeng:inst\|current_state\" contains 8 states" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "State machine \"%1!s!\" contains %2!d! states" 0 0}
{ "Info" "IOPT_SMP_MACHINE_REPORT_PROCESSOR" "Auto \|dingceng\|jiaotongdeng:inst\|current_state " "Info: Selected Auto state machine encoding method for state machine \"\|dingceng\|jiaotongdeng:inst\|current_state\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "Selected %1!s! state machine encoding method for state machine \"%2!s!\"" 0 0}
{ "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_HEADER" "\|dingceng\|jiaotongdeng:inst\|current_state " "Info: Encoding result for state machine \"\|dingceng\|jiaotongdeng:inst\|current_state\"" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS_HEADER" "3 " "Info: Completed encoding using 3 state bits" { { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiaotongdeng:inst\|current_state~16 " "Info: Encoded state bit \"jiaotongdeng:inst\|current_state~16\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiaotongdeng:inst\|current_state~15 " "Info: Encoded state bit \"jiaotongdeng:inst\|current_state~15\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_BITS" "jiaotongdeng:inst\|current_state~14 " "Info: Encoded state bit \"jiaotongdeng:inst\|current_state~14\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "Encoded state bit \"%1!s!\"" 0 0}  } {  } 0 0 "Completed encoding using %1!d! state bits" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dingceng\|jiaotongdeng:inst\|current_state.state0 000 " "Info: State \"\|dingceng\|jiaotongdeng:inst\|current_state.state0\" uses code string \"000\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dingceng\|jiaotongdeng:inst\|current_state.state6 110 " "Info: State \"\|dingceng\|jiaotongdeng:inst\|current_state.state6\" uses code string \"110\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dingceng\|jiaotongdeng:inst\|current_state.state5 101 " "Info: State \"\|dingceng\|jiaotongdeng:inst\|current_state.state5\" uses code string \"101\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dingceng\|jiaotongdeng:inst\|current_state.state4 100 " "Info: State \"\|dingceng\|jiaotongdeng:inst\|current_state.state4\" uses code string \"100\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dingceng\|jiaotongdeng:inst\|current_state.state3 011 " "Info: State \"\|dingceng\|jiaotongdeng:inst\|current_state.state3\" uses code string \"011\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dingceng\|jiaotongdeng:inst\|current_state.state2 010 " "Info: State \"\|dingceng\|jiaotongdeng:inst\|current_state.state2\" uses code string \"010\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dingceng\|jiaotongdeng:inst\|current_state.state1 001 " "Info: State \"\|dingceng\|jiaotongdeng:inst\|current_state.state1\" uses code string \"001\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0} { "Info" "IOPT_SMP_MACHINE_POSTPROCESS_STAT_CODE" "\|dingceng\|jiaotongdeng:inst\|current_state.state7 111 " "Info: State \"\|dingceng\|jiaotongdeng:inst\|current_state.state7\" uses code string \"111\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "State \"%1!s!\" uses code string \"%2!s!\"" 0 0}  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 7 -1 0 } }  } 0 0 "Encoding result for state machine \"%1!s!\"" 0 0}
{ "Info" "IOPT_MLS_IGNORED_SUMMARY" "26 " "Info: Ignored 26 buffer(s)" { { "Info" "IOPT_MLS_IGNORED_SOFT" "26 " "Info: Ignored 26 SOFT buffer(s)" {  } {  } 0 0 "Ignored %1!d! SOFT buffer(s)" 0 0}  } {  } 0 0 "Ignored %1!d! buffer(s)" 0 0}
{ "Info" "IOPT_MLS_DUP_REG_INFO_HDR" "" "Info: Duplicate registers merged to single register" { { "Info" "IOPT_MLS_DUP_REG_INFO" "jiaotongdeng:inst\|count\[0\] xianshi:inst1\|lpm_counter:count_rtl_0\|dffs\[0\] " "Info: Duplicate register \"jiaotongdeng:inst\|count\[0\]\" merged to single register \"xianshi:inst1\|lpm_counter:count_rtl_0\|dffs\[0\]\"" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 25 -1 0 } }  } 0 0 "Duplicate register \"%1!s!\" merged to single register \"%2!s!\"" 0 0}  } {  } 0 0 "Duplicate registers merged to single register" 0 0}
{ "Warning" "WOPT_MLS_STUCK_PIN_HDR" "" "Warning: Output pins are stuck at VCC or GND" { { "Warning" "WOPT_MLS_STUCK_PIN" "seg\[7\] VCC " "Warning: Pin \"seg\[7\]\" stuck at VCC" {  } { { "dingceng.bdf" "" { Schematic "F:/My_design/jiaotongdeng/dingceng.bdf" { { 96 648 824 112 "seg\[7..0\]" "" } } } }  } 0 0 "Pin \"%1!s!\" stuck at %2!s!" 0 0}  } {  } 0 0 "Output pins are stuck at VCC or GND" 0 0}
{ "Info" "IMTM_MTM_PROMOTE_GLOBAL" "" "Info: Promoted pin-driven signal(s) to global signal" { { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLOCK" "CLK " "Info: Promoted clock signal driven by pin \"CLK\" to global clock signal" {  } {  } 0 0 "Promoted clock signal driven by pin \"%1!s!\" to global clock signal" 0 0} { "Info" "IMTM_MTM_PROMOTE_GLOBAL_CLEAR" "ST " "Info: Promoted clear signal driven by pin \"ST\" to global clear signal" {  } {  } 0 0 "Promoted clear signal driven by pin \"%1!s!\" to global clear signal" 0 0}  } {  } 0 0 "Promoted pin-driven signal(s) to global signal" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "102 " "Info: Implemented 102 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "2 " "Info: Implemented 2 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "18 " "Info: Implemented 18 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_MCELLS" "78 " "Info: Implemented 78 macrocells" {  } {  } 0 0 "Implemented %1!d! macrocells" 0 0} { "Info" "ISCL_SCL_TM_SEXPS" "4 " "Info: Implemented 4 shareable expanders" {  } {  } 0 0 "Implemented %1!d! shareable expanders" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 12 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 12 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Mon Jun 23 18:01:17 2008 " "Info: Processing ended: Mon Jun 23 18:01:17 2008" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:05 " "Info: Elapsed time: 00:00:05" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}