jiaotongdeng.map.qmsg

用Verilog HDL语言编写的交通灯程序

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.1 Build 176 10/26/2005 SJ Full Version " "Info: Version 5.1 Build 176 10/26/2005 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Mon Jun 23 18:01:12 2008 " "Info: Processing started: Mon Jun 23 18:01:12 2008" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off jiaotongdeng -c jiaotongdeng " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off jiaotongdeng -c jiaotongdeng" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "dingceng.bdf 1 1 " "Info: Found 1 design units, including 1 entities, in source file dingceng.bdf" { { "Info" "ISGN_ENTITY_NAME" "1 dingceng " "Info: Found entity 1: dingceng" {  } { { "dingceng.bdf" "" { Schematic "F:/My_design/jiaotongdeng/dingceng.bdf" { } } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "jiaotongdeng.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file jiaotongdeng.v" { { "Info" "ISGN_ENTITY_NAME" "1 jiaotongdeng " "Info: Found entity 1: jiaotongdeng" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "dingceng " "Info: Elaborating entity \"dingceng\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "jiaotongdeng jiaotongdeng:inst " "Info: Elaborating entity \"jiaotongdeng\" for hierarchy \"jiaotongdeng:inst\"" {  } { { "dingceng.bdf" "inst" { Schematic "F:/My_design/jiaotongdeng/dingceng.bdf" { { 72 200 392 168 "inst" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "ared jiaotongdeng.v(13) " "Warning (10036): Verilog HDL or VHDL warning at jiaotongdeng.v(13): object \"ared\" assigned a value but never read" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 13 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VRFC_OBJECT_ASSIGNED_NOT_READ" "bred jiaotongdeng.v(14) " "Warning (10036): Verilog HDL or VHDL warning at jiaotongdeng.v(14): object \"bred\" assigned a value but never read" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 14 0 0 } }  } 0 10036 "Verilog HDL or VHDL warning at %2!s!: object \"%1!s!\" assigned a value but never read" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 26 jiaotongdeng.v(19) " "Warning (10230): Verilog HDL assignment warning at jiaotongdeng.v(19): truncated value with size 32 to match size of target (26)" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 19 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 1 jiaotongdeng.v(23) " "Warning (10230): Verilog HDL assignment warning at jiaotongdeng.v(23): truncated value with size 32 to match size of target (1)" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 23 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jiaotongdeng.v(52) " "Warning (10230): Verilog HDL assignment warning at jiaotongdeng.v(52): truncated value with size 32 to match size of target (4)" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 52 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 4 jiaotongdeng.v(57) " "Warning (10230): Verilog HDL assignment warning at jiaotongdeng.v(57): truncated value with size 32 to match size of target (4)" {  } { { "jiaotongdeng.v" "" { Text "F:/My_design/jiaotongdeng/jiaotongdeng.v" 57 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WSGN_SEARCH_FILE" "xianshi.v 1 1 " "Warning: Using design file xianshi.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project" { { "Info" "ISGN_ENTITY_NAME" "1 xianshi " "Info: Found entity 1: xianshi" {  } { { "xianshi.v" "" { Text "F:/My_design/jiaotongdeng/xianshi.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Using design file %1!s!, which is not specified as a design file for the current project, but contains definitions for %2!d! design units and %3!d! entities in project" 0 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "xianshi xianshi:inst1 " "Info: Elaborating entity \"xianshi\" for hierarchy \"xianshi:inst1\"" {  } { { "dingceng.bdf" "inst1" { Schematic "F:/My_design/jiaotongdeng/dingceng.bdf" { { 72 440 608 168 "inst1" "" } } } }  } 0 0 "Elaborating entity \"%1!s!\" for hierarchy \"%2!s!\"" 0 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 13 xianshi.v(12) " "Warning (10230): Verilog HDL assignment warning at xianshi.v(12): truncated value with size 32 to match size of target (13)" {  } { { "xianshi.v" "" { Text "F:/My_design/jiaotongdeng/xianshi.v" 12 0 0 } }  } 0 10230 "Verilog HDL assignment warning at %3!s!: truncated value with size %1!d! to match size of target (%2!d!)" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "temp_reg xianshi.v(17) " "Warning (10235): Verilog HDL Always Construct warning at xianshi.v(17): variable \"temp_reg\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "xianshi.v" "" { Text "F:/My_design/jiaotongdeng/xianshi.v" 17 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}
{ "Warning" "WVRFX_VERI_INCOMPLETE_SENSITIVITY_LIST" "temp_reg xianshi.v(18) " "Warning (10235): Verilog HDL Always Construct warning at xianshi.v(18): variable \"temp_reg\" is read inside the Always Construct but isn't in the Always Construct's Event Control" {  } { { "xianshi.v" "" { Text "F:/My_design/jiaotongdeng/xianshi.v" 18 0 0 } }  } 0 10235 "Verilog HDL Always Construct warning at %2!s!: variable \"%1!s!\" is read inside the Always Construct but isn't in the Always Construct's Event Control" 0 0}