dingceng.sim.rpt

用Verilog HDL语言编写的交通灯程序

; |jiaotongdeng|count_down[0]           ; |jiaotongdeng|count_down[0]           ; padio            ;
; |jiaotongdeng|count_down[1]           ; |jiaotongdeng|count_down[1]           ; padio            ;
; |jiaotongdeng|count_down[2]           ; |jiaotongdeng|count_down[2]           ; padio            ;
; |jiaotongdeng|count_down[3]           ; |jiaotongdeng|count_down[3]           ; padio            ;
; |jiaotongdeng|count_down[4]           ; |jiaotongdeng|count_down[4]           ; padio            ;
; |jiaotongdeng|count_down[5]           ; |jiaotongdeng|count_down[5]           ; padio            ;
; |jiaotongdeng|count_down[6]           ; |jiaotongdeng|count_down[6]           ; padio            ;
; |jiaotongdeng|LAMP[4]                 ; |jiaotongdeng|LAMP[4]                 ; padio            ;
; |jiaotongdeng|LAMP[6]                 ; |jiaotongdeng|LAMP[6]                 ; padio            ;
+---------------------------------------+---------------------------------------+------------------+


The following table displays output ports that do not toggle to 1 during simulation.
+--------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage                                                                         ;
+---------------------------------------+---------------------------------------+------------------+
; Node Name                             ; Output Port Name                      ; Output Port Type ;
+---------------------------------------+---------------------------------------+------------------+
; |jiaotongdeng|count[5]                ; |jiaotongdeng|count[5]                ; dataout          ;
; |jiaotongdeng|count[6]                ; |jiaotongdeng|count[6]                ; dataout          ;
; |jiaotongdeng|count[7]                ; |jiaotongdeng|count[7]                ; dataout          ;
; |jiaotongdeng|count[8]                ; |jiaotongdeng|count[8]                ; dataout          ;
; |jiaotongdeng|count[9]                ; |jiaotongdeng|count[9]                ; dataout          ;
; |jiaotongdeng|count[10]               ; |jiaotongdeng|count[10]               ; dataout          ;
; |jiaotongdeng|count[11]               ; |jiaotongdeng|count[11]               ; dataout          ;
; |jiaotongdeng|count[12]               ; |jiaotongdeng|count[12]               ; dataout          ;
; |jiaotongdeng|count[13]               ; |jiaotongdeng|count[13]               ; dataout          ;
; |jiaotongdeng|count[14]               ; |jiaotongdeng|count[14]               ; dataout          ;
; |jiaotongdeng|count[15]               ; |jiaotongdeng|count[15]               ; dataout          ;
; |jiaotongdeng|count[16]               ; |jiaotongdeng|count[16]               ; dataout          ;
; |jiaotongdeng|count[17]               ; |jiaotongdeng|count[17]               ; dataout          ;
; |jiaotongdeng|count[18]               ; |jiaotongdeng|count[18]               ; dataout          ;
; |jiaotongdeng|count[19]               ; |jiaotongdeng|count[19]               ; dataout          ;
; |jiaotongdeng|count[20]               ; |jiaotongdeng|count[20]               ; dataout          ;
; |jiaotongdeng|count[21]               ; |jiaotongdeng|count[21]               ; dataout          ;
; |jiaotongdeng|count[22]               ; |jiaotongdeng|count[22]               ; dataout          ;
; |jiaotongdeng|count[23]               ; |jiaotongdeng|count[23]               ; dataout          ;
; |jiaotongdeng|count[24]               ; |jiaotongdeng|count[24]               ; dataout          ;
; |jiaotongdeng|count_down[7]~reg0      ; |jiaotongdeng|count_down[7]~reg0      ; dataout          ;
; |jiaotongdeng|current_state.state6~39 ; |jiaotongdeng|current_state.state6~39 ; dataout          ;
; |jiaotongdeng|current_state.state4~30 ; |jiaotongdeng|current_state.state4~30 ; dataout          ;
; |jiaotongdeng|current_state.state7~10 ; |jiaotongdeng|current_state.state7~10 ; dataout          ;
; |jiaotongdeng|current_state~186       ; |jiaotongdeng|current_state~186       ; dataout          ;
; |jiaotongdeng|count_down[7]           ; |jiaotongdeng|count_down[7]           ; padio            ;
; |jiaotongdeng|LAMP[0]                 ; |jiaotongdeng|LAMP[0]                 ; padio            ;
; |jiaotongdeng|LAMP[1]                 ; |jiaotongdeng|LAMP[1]                 ; padio            ;
; |jiaotongdeng|LAMP[2]                 ; |jiaotongdeng|LAMP[2]                 ; padio            ;
; |jiaotongdeng|LAMP[7]                 ; |jiaotongdeng|LAMP[7]                 ; padio            ;
+---------------------------------------+---------------------------------------+------------------+


The following table displays output ports that do not toggle to 0 during simulation.
+--------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage                                                                         ;
+---------------------------------------+---------------------------------------+------------------+
; Node Name                             ; Output Port Name                      ; Output Port Type ;
+---------------------------------------+---------------------------------------+------------------+
; |jiaotongdeng|count[5]                ; |jiaotongdeng|count[5]                ; dataout          ;
; |jiaotongdeng|count[6]                ; |jiaotongdeng|count[6]                ; dataout          ;
; |jiaotongdeng|count[7]                ; |jiaotongdeng|count[7]                ; dataout          ;
; |jiaotongdeng|count[8]                ; |jiaotongdeng|count[8]                ; dataout          ;
; |jiaotongdeng|count[9]                ; |jiaotongdeng|count[9]                ; dataout          ;
; |jiaotongdeng|count[10]               ; |jiaotongdeng|count[10]               ; dataout          ;
; |jiaotongdeng|count[11]               ; |jiaotongdeng|count[11]               ; dataout          ;
; |jiaotongdeng|count[12]               ; |jiaotongdeng|count[12]               ; dataout          ;
; |jiaotongdeng|count[13]               ; |jiaotongdeng|count[13]               ; dataout          ;
; |jiaotongdeng|count[14]               ; |jiaotongdeng|count[14]               ; dataout          ;
; |jiaotongdeng|count[15]               ; |jiaotongdeng|count[15]               ; dataout          ;
; |jiaotongdeng|count[16]               ; |jiaotongdeng|count[16]               ; dataout          ;
; |jiaotongdeng|count[17]               ; |jiaotongdeng|count[17]               ; dataout          ;
; |jiaotongdeng|count[18]               ; |jiaotongdeng|count[18]               ; dataout          ;
; |jiaotongdeng|count[19]               ; |jiaotongdeng|count[19]               ; dataout          ;
; |jiaotongdeng|count[20]               ; |jiaotongdeng|count[20]               ; dataout          ;
; |jiaotongdeng|count[21]               ; |jiaotongdeng|count[21]               ; dataout          ;
; |jiaotongdeng|count[22]               ; |jiaotongdeng|count[22]               ; dataout          ;
; |jiaotongdeng|count[23]               ; |jiaotongdeng|count[23]               ; dataout          ;
; |jiaotongdeng|count[24]               ; |jiaotongdeng|count[24]               ; dataout          ;
; |jiaotongdeng|count_down[7]~reg0      ; |jiaotongdeng|count_down[7]~reg0      ; dataout          ;
; |jiaotongdeng|current_state~16        ; |jiaotongdeng|current_state~16        ; dataout          ;
; |jiaotongdeng|current_state.state0~27 ; |jiaotongdeng|current_state.state0~27 ; dataout          ;
; |jiaotongdeng|current_state.state6~39 ; |jiaotongdeng|current_state.state6~39 ; dataout          ;
; |jiaotongdeng|current_state.state7~10 ; |jiaotongdeng|current_state.state7~10 ; dataout          ;
; |jiaotongdeng|EN                      ; |jiaotongdeng|EN                      ; dataout          ;
; |jiaotongdeng|count_down[7]           ; |jiaotongdeng|count_down[7]           ; padio            ;
; |jiaotongdeng|LAMP[0]                 ; |jiaotongdeng|LAMP[0]                 ; padio            ;
; |jiaotongdeng|LAMP[2]                 ; |jiaotongdeng|LAMP[2]                 ; padio            ;
; |jiaotongdeng|LAMP[3]                 ; |jiaotongdeng|LAMP[3]                 ; padio            ;
; |jiaotongdeng|LAMP[5]                 ; |jiaotongdeng|LAMP[5]                 ; padio            ;
+---------------------------------------+---------------------------------------+------------------+


+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage      ;
+--------+------------+


+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
    Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
    Info: Processing started: Mon Jun 23 17:51:23 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off dingceng -c dingceng
Warning: Compiler packed, optimized or synthesized away node "seg[7]". Ignored vector source file node.
Warning: Compiler packed, optimized or synthesized away node "seg[6]". Ignored vector source file node.
Warning: Compiler packed, optimized or synthesized away node "seg[5]". Ignored vector source file node.
Warning: Compiler packed, optimized or synthesized away node "seg[4]". Ignored vector source file node.
Warning: Compiler packed, optimized or synthesized away node "seg[3]". Ignored vector source file node.
Warning: Compiler packed, optimized or synthesized away node "seg[2]". Ignored vector source file node.
Warning: Compiler packed, optimized or synthesized away node "seg[1]". Ignored vector source file node.
Warning: Compiler packed, optimized or synthesized away node "seg[0]". Ignored vector source file node.
Warning: Compiler packed, optimized or synthesized away node "sl[1]". Ignored vector source file node.
Warning: Compiler packed, optimized or synthesized away node "sl[0]". Ignored vector source file node.
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
    Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is      47.76 %
Info: Number of transitions in simulation is 20247
Info: Quartus II Simulator was successful. 0 errors, 10 warnings
    Info: Processing ended: Mon Jun 23 17:51:28 2008
    Info: Elapsed time: 00:00:05