📄 jiaotongdeng.sim.rpt
字号:
; |dingceng|xianshi:inst1|reduce_or~1735 ; |dingceng|xianshi:inst1|reduce_or~1735 ; dataout ;
; |dingceng|xianshi:inst1|reduce_or~1741 ; |dingceng|xianshi:inst1|reduce_or~1741 ; dataout ;
; |dingceng|xianshi:inst1|reduce_or~1748 ; |dingceng|xianshi:inst1|reduce_or~1748 ; dataout ;
; |dingceng|xianshi:inst1|reduce_or~1749 ; |dingceng|xianshi:inst1|reduce_or~1749 ; dataout ;
; |dingceng|xianshi:inst1|reduce_or~1750 ; |dingceng|xianshi:inst1|reduce_or~1750 ; dataout ;
; |dingceng|xianshi:inst1|reduce_or~1751 ; |dingceng|xianshi:inst1|reduce_or~1751 ; dataout ;
; |dingceng|xianshi:inst1|reduce_or~1752 ; |dingceng|xianshi:inst1|reduce_or~1752 ; dataout ;
; |dingceng|xianshi:inst1|reduce_or~1757 ; |dingceng|xianshi:inst1|reduce_or~1757 ; dataout ;
; |dingceng|xianshi:inst1|reduce_or~1765 ; |dingceng|xianshi:inst1|reduce_or~1765 ; dataout ;
; |dingceng|xianshi:inst1|reduce_or~1770 ; |dingceng|xianshi:inst1|reduce_or~1770 ; dataout ;
; |dingceng|jiaotongdeng:inst|current_state~16 ; |dingceng|jiaotongdeng:inst|current_state~16 ; dataout ;
; |dingceng|jiaotongdeng:inst|current_state.state7~10 ; |dingceng|jiaotongdeng:inst|current_state.state7~10 ; dataout ;
; |dingceng|jiaotongdeng:inst|current_state.state3~31 ; |dingceng|jiaotongdeng:inst|current_state.state3~31 ; dataout ;
; |dingceng|jiaotongdeng:inst|current_state~182 ; |dingceng|jiaotongdeng:inst|current_state~182 ; dataout ;
; |dingceng|jiaotongdeng:inst|count_down[2]~469 ; |dingceng|jiaotongdeng:inst|count_down[2]~469 ; pexpout ;
; |dingceng|jiaotongdeng:inst|count_down[3]~471 ; |dingceng|jiaotongdeng:inst|count_down[3]~471 ; pexpout ;
; |dingceng|jiaotongdeng:inst|count_down[4]~474 ; |dingceng|jiaotongdeng:inst|count_down[4]~474 ; pexpout ;
; |dingceng|jiaotongdeng:inst|count_down[5]~479 ; |dingceng|jiaotongdeng:inst|count_down[5]~479 ; pexpout ;
; |dingceng|jiaotongdeng:inst|count_down[6]~483 ; |dingceng|jiaotongdeng:inst|count_down[6]~483 ; pexpout ;
; |dingceng|xianshi:inst1|reduce_or~1778 ; |dingceng|xianshi:inst1|reduce_or~1778 ; pexpout ;
; |dingceng|xianshi:inst1|reduce_or~1782 ; |dingceng|xianshi:inst1|reduce_or~1782 ; pexpout ;
; |dingceng|xianshi:inst1|reduce_or~1786 ; |dingceng|xianshi:inst1|reduce_or~1786 ; pexpout ;
; |dingceng|CLK ; |dingceng|CLK ; dataout ;
; |dingceng|LAMP[5] ; |dingceng|LAMP[5] ; padio ;
; |dingceng|LAMP[4] ; |dingceng|LAMP[4] ; padio ;
; |dingceng|LAMP[1] ; |dingceng|LAMP[1] ; padio ;
; |dingceng|LAMP[0] ; |dingceng|LAMP[0] ; padio ;
; |dingceng|sl[1] ; |dingceng|sl[1] ; padio ;
; |dingceng|sl[0] ; |dingceng|sl[0] ; padio ;
; |dingceng|seg[6] ; |dingceng|seg[6] ; padio ;
; |dingceng|seg[2] ; |dingceng|seg[2] ; padio ;
; |dingceng|seg[1] ; |dingceng|seg[1] ; padio ;
; |dingceng|seg[5] ; |dingceng|seg[5] ; padio ;
; |dingceng|seg[0] ; |dingceng|seg[0] ; padio ;
; |dingceng|seg[4] ; |dingceng|seg[4] ; padio ;
; |dingceng|seg[3] ; |dingceng|seg[3] ; padio ;
; |dingceng|LAMP[7] ; |dingceng|LAMP[7] ; padio ;
; |dingceng|LAMP[6] ; |dingceng|LAMP[6] ; padio ;
; |dingceng|LAMP[3] ; |dingceng|LAMP[3] ; padio ;
; |dingceng|LAMP[2] ; |dingceng|LAMP[2] ; padio ;
+-------------------------------------------------------------+-------------------------------------------------------------+------------------+
The following table displays output ports that do not toggle to 1 during simulation.
+----------------------------------------------------------------------------------------------------------+
; Missing 1-Value Coverage ;
+-------------------------------------------+-------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------------------+-------------------------------------------+------------------+
; |dingceng|jiaotongdeng:inst|count[5] ; |dingceng|jiaotongdeng:inst|count[5] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[6] ; |dingceng|jiaotongdeng:inst|count[6] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[7] ; |dingceng|jiaotongdeng:inst|count[7] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[8] ; |dingceng|jiaotongdeng:inst|count[8] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[9] ; |dingceng|jiaotongdeng:inst|count[9] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[10] ; |dingceng|jiaotongdeng:inst|count[10] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[11] ; |dingceng|jiaotongdeng:inst|count[11] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[12] ; |dingceng|jiaotongdeng:inst|count[12] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[13] ; |dingceng|jiaotongdeng:inst|count[13] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[14] ; |dingceng|jiaotongdeng:inst|count[14] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[15] ; |dingceng|jiaotongdeng:inst|count[15] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[16] ; |dingceng|jiaotongdeng:inst|count[16] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[17] ; |dingceng|jiaotongdeng:inst|count[17] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[18] ; |dingceng|jiaotongdeng:inst|count[18] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[19] ; |dingceng|jiaotongdeng:inst|count[19] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[20] ; |dingceng|jiaotongdeng:inst|count[20] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[21] ; |dingceng|jiaotongdeng:inst|count[21] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[22] ; |dingceng|jiaotongdeng:inst|count[22] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[23] ; |dingceng|jiaotongdeng:inst|count[23] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[24] ; |dingceng|jiaotongdeng:inst|count[24] ; dataout ;
; |dingceng|jiaotongdeng:inst|count_down[7] ; |dingceng|jiaotongdeng:inst|count_down[7] ; dataout ;
; |dingceng|xianshi:inst1|reduce_or~1772 ; |dingceng|xianshi:inst1|reduce_or~1772 ; pexpout ;
; |dingceng|xianshi:inst1|reduce_or~1774 ; |dingceng|xianshi:inst1|reduce_or~1774 ; pexpout ;
; |dingceng|~VCC~0 ; |dingceng|~VCC~0 ; dataout ;
; |dingceng|seg[7] ; |dingceng|seg[7] ; padio ;
+-------------------------------------------+-------------------------------------------+------------------+
The following table displays output ports that do not toggle to 0 during simulation.
+----------------------------------------------------------------------------------------------------------+
; Missing 0-Value Coverage ;
+-------------------------------------------+-------------------------------------------+------------------+
; Node Name ; Output Port Name ; Output Port Type ;
+-------------------------------------------+-------------------------------------------+------------------+
; |dingceng|jiaotongdeng:inst|count[5] ; |dingceng|jiaotongdeng:inst|count[5] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[6] ; |dingceng|jiaotongdeng:inst|count[6] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[7] ; |dingceng|jiaotongdeng:inst|count[7] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[8] ; |dingceng|jiaotongdeng:inst|count[8] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[9] ; |dingceng|jiaotongdeng:inst|count[9] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[10] ; |dingceng|jiaotongdeng:inst|count[10] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[11] ; |dingceng|jiaotongdeng:inst|count[11] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[12] ; |dingceng|jiaotongdeng:inst|count[12] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[13] ; |dingceng|jiaotongdeng:inst|count[13] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[14] ; |dingceng|jiaotongdeng:inst|count[14] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[15] ; |dingceng|jiaotongdeng:inst|count[15] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[16] ; |dingceng|jiaotongdeng:inst|count[16] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[17] ; |dingceng|jiaotongdeng:inst|count[17] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[18] ; |dingceng|jiaotongdeng:inst|count[18] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[19] ; |dingceng|jiaotongdeng:inst|count[19] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[20] ; |dingceng|jiaotongdeng:inst|count[20] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[21] ; |dingceng|jiaotongdeng:inst|count[21] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[22] ; |dingceng|jiaotongdeng:inst|count[22] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[23] ; |dingceng|jiaotongdeng:inst|count[23] ; dataout ;
; |dingceng|jiaotongdeng:inst|count[24] ; |dingceng|jiaotongdeng:inst|count[24] ; dataout ;
; |dingceng|jiaotongdeng:inst|count_down[7] ; |dingceng|jiaotongdeng:inst|count_down[7] ; dataout ;
; |dingceng|xianshi:inst1|reduce_or~1772 ; |dingceng|xianshi:inst1|reduce_or~1772 ; pexpout ;
; |dingceng|xianshi:inst1|reduce_or~1774 ; |dingceng|xianshi:inst1|reduce_or~1774 ; pexpout ;
; |dingceng|~VCC~0 ; |dingceng|~VCC~0 ; dataout ;
; |dingceng|ST ; |dingceng|ST ; dataout ;
; |dingceng|seg[7] ; |dingceng|seg[7] ; padio ;
+-------------------------------------------+-------------------------------------------+------------------+
+---------------------+
; Simulator INI Usage ;
+--------+------------+
; Option ; Usage ;
+--------+------------+
+--------------------+
; Simulator Messages ;
+--------------------+
Info: *******************************************************************
Info: Running Quartus II Simulator
Info: Version 5.1 Build 176 10/26/2005 SJ Full Version
Info: Processing started: Mon Jun 23 18:02:18 2008
Info: Command: quartus_sim --read_settings_files=on --write_settings_files=off jiaotongdeng -c jiaotongdeng
Info: Option to preserve fewer signal transitions to reduce memory requirements is enabled
Info: Simulation has been partitioned into sub-simulations according to the maximum transition count determined by the engine. Transitions from memory will be flushed out to disk at the end of each sub-simulation to reduce memory requirements.
Info: Simulation partitioned into 1 sub-simulations
Info: Simulation coverage is 74.00 %
Info: Number of transitions in simulation is 51476
Info: Quartus II Simulator was successful. 0 errors, 0 warnings
Info: Processing ended: Mon Jun 23 18:02:25 2008
Info: Elapsed time: 00:00:07
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