dingceng.qsf

用Verilog HDL语言编写的交通灯程序

# Copyright (C) 1991-2005 Altera Corporation
# Your use of Altera Corporation's design tools, logic functions 
# and other software and tools, and its AMPP partner logic 
# functions, and any output files any of the foregoing 
# (including device programming or simulation files), and any 
# associated documentation or information are expressly subject 
# to the terms and conditions of the Altera Program License 
# Subscription Agreement, Altera MegaCore Function License 
# Agreement, or other applicable license agreement, including, 
# without limitation, that your use is for the sole purpose of 
# programming logic devices manufactured by Altera and sold by 
# Altera or its authorized distributors.  Please refer to the 
# applicable agreement for further details.


# The default values for assignments are stored in the file
#		dingceng_assignment_defaults.qdf
# If this file doesn't exist, and for assignments not listed, see file
#		assignment_defaults.qdf

# Altera recommends that you do not modify this file. This
# file is updated automatically by the Quartus II software
# and any changes you make may be lost or overwritten.


set_global_assignment -name FAMILY MAX7000S
set_global_assignment -name DEVICE "EPM7128SLC84-15"
set_global_assignment -name TOP_LEVEL_ENTITY jiaotongdeng
set_global_assignment -name ORIGINAL_QUARTUS_VERSION 5.1
set_global_assignment -name PROJECT_CREATION_TIME_DATE "17:03:54  APRIL 24, 2008"
set_global_assignment -name LAST_QUARTUS_VERSION 5.1
set_global_assignment -name DEVICE_FILTER_PIN_COUNT 84
set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 15
set_location_assignment PIN_83 -to clk
set_location_assignment PIN_52 -to seg[7]
set_location_assignment PIN_51 -to seg[6]
set_location_assignment PIN_50 -to seg[5]
set_location_assignment PIN_49 -to seg[4]
set_location_assignment PIN_48 -to seg[3]
set_location_assignment PIN_46 -to seg[2]
set_location_assignment PIN_45 -to seg[1]
set_location_assignment PIN_44 -to seg[0]
set_location_assignment PIN_33 -to sl[0]
set_location_assignment PIN_34 -to sl[1]
set_global_assignment -name VERILOG_FILE jiaotongdeng.v
set_global_assignment -name VERILOG_FILE xianshi.v
set_global_assignment -name BDF_FILE dingceng.bdf
set_global_assignment -name VECTOR_WAVEFORM_FILE dingceng.vwf
set_location_assignment PIN_74 -to ST
set_location_assignment PIN_54 -to LAMP[7]
set_location_assignment PIN_55 -to LAMP[6]
set_location_assignment PIN_56 -to LAMP[5]
set_location_assignment PIN_57 -to LAMP[4]
set_location_assignment PIN_58 -to LAMP[3]
set_location_assignment PIN_60 -to LAMP[2]
set_location_assignment PIN_61 -to LAMP[1]
set_location_assignment PIN_63 -to LAMP[0]