jiaotongdeng.v

用Verilog HDL语言编写的交通灯程序

module jiaotongdeng(CLK,EN,LAMP,count_down);
	input  CLK,EN;
	output[7:0]LAMP;    //LAMP[3:0]主干道 红、黄、直行绿灯、左拐绿灯
						//LAMP[7:4]支干道 红、黄、直行绿灯、左拐绿灯
	output[7:0]count_down;						
	reg[7:0]LAMP;
	reg[7:0]current_state,next_state;
	reg CLK1;
	reg CLK2;
	reg temp; 
	reg[25:0]count;  		
	reg[7:0]count_down;	//倒计时
	parameter[7:0]ared=8'h55,yerrow=8'h5,agreen=8'h40,aleft=8'h15, //主干道各灯点亮时间
	              bred=8'h65,bgreen=8'h30,bleft=8'h15; //支干道各灯点亮时间
	parameter[7:0]state0=0,state1=1,state2=2,state3=3,
				  state4=4,state5=5,state6=6,state7=7;
  always@(posedge CLK)
	begin 
		count<=count+1;
		if(count==25)
		begin
			count<=0;
			CLK2<=CLK2+1;
		end
	end
  always@(posedge CLK2)
	begin
		if(!EN)
			begin temp<=0;end
		else if(!temp)
			begin
				temp<=1;
				case(current_state)
					state0:begin count_down<=agreen;end
					state1:begin count_down<=yerrow;end
					state2:begin count_down<=aleft;end
					state3:begin count_down<=yerrow;end
					state4:begin count_down<=bgreen;end
					state5:begin count_down<=yerrow;end
					state6:begin count_down<=bleft;end
					state7:begin count_down<=yerrow;end
					default:begin count_down<=agreen;end
				endcase	
			end
		else
			begin
				if(count_down==0)
					begin CLK1<=1;temp<=0;end
				else if(count_down[3:0]==0)
					begin
					count_down[3:0] <= 9;
					count_down[7:4] <= count_down[7:4]-1;
					CLK1<=0;
					end
				else
					begin
					count_down[3:0] <= count_down[3:0]-1;
					CLK1<=0;
					end
			end
	end
  always@(posedge CLK1 or negedge EN)
	begin
		if(!EN)current_state<=state0;
		else current_state<=next_state;
	end
  always@(current_state)
	begin
		case(current_state)
			state0:begin next_state<=state1;end
			state1:begin next_state<=state2;end
			state2:begin next_state<=state3;end
			state3:begin next_state<=state4;end
			state4:begin next_state<=state5;end
			state5:begin next_state<=state6;end
			state6:begin next_state<=state7;end
			state7:begin next_state<=state0;end
			default:next_state<=state0;
		endcase	
	end
	always@(current_state)
		begin
			case(current_state)
				state0:begin LAMP<=8'h28;end//40s
				state1:begin LAMP<=8'h48;end//5s
				state2:begin LAMP<=8'h18;end//15s
				state3:begin LAMP<=8'h48;end//5
				state4:begin LAMP<=8'h82;end//
				state5:begin LAMP<=8'h84;end
				state6:begin LAMP<=8'h81;end
				state7:begin LAMP<=8'h84;end
			endcase		
		end
endmodule