regs54xx.h

5416完整例程

#define RINT1_VEC		   104
#define XINT1_VEC		   108
#define DMAC2_VEC		   104
#define DMAC3_VEC		   108
#define DMAC4_VEC		   112
#define DMAC5_VEC		   116


/*********************************************************************/
/* Define data structures for all memory mapped registers            */
/*********************************************************************/
/*----------------------------------------------------------------*/
/* Data bitfields Period for Timer                                */
/*----------------------------------------------------------------*/
#define PSC		       6
#define PSC_SZ		 4

#define TRB			 5
#define TRB_SZ		 1

#define TSS			 4
#define TSS_SZ		 1

#define TDDR		 0
#define TDDR_SZ		 4

/*---------------------------------------------------------------*/
/* Data bitfields for Clock Mode Register                        */
/*---------------------------------------------------------------*/
#define PLLMUL		12
#define PLLMUL_SZ	 	4

#define PLLDIV		11
#define PLLDIV_SZ	 	1

#define PLLCOUNT	 	3
#define PLLCOUNT_SZ	8

#define PLLON_OFF	 	2
#define PLLON_OFF_SZ 	1

#define PLLNDIV		1
#define PLLNDIV_SZ	1

#define PLLSTATUS	 	0
#define PLLSTATUS_SZ 	1


/*----------------------------------------------------------------*/
/* Define bit fields for Software Wait State Register             */
/*----------------------------------------------------------------*/
#define IO		    	12
#define IO_SZ		 3

#define DATA_HI		 9
#define DATA_HI_SZ	 3

#define DATA_LO		 6
#define DATA_LO_SZ	 3

#define PROGRAM_HI	 3
#define PROGRAM_HI_SZ	 3

#define PROGRAM_LO	 0
#define PROGRAM_LO_SZ	 3

/*-------------------------------------------------------------------*/
/* Define bitfields for Bank Switch Control Register                 */
/*-------------------------------------------------------------------*/
#define BNKCMP		12
#define BNKCMP_SZ	 	4

#define PS_DS		11
#define PS_DS_SZ	 	1

#define HBH		     	 2
#define HBH_SZ		 1

#define BH		     	 1
#define BH_SZ		 1

#define EXIO		     	 0
#define EXIO_SZ		 1

/*-------------------------------------------------------------------*/
/* Define bitfields for Interruput Mask Register                     */
/*-------------------------------------------------------------------*/
#define INT0		 0
#define INT1		 1
#define INT2		 2
#define TINT0		 3

#define RINT0		 4
#define XINT0		 5

#define TINT1		 7

#define INT3		 8
#define HPINT		 9
#define RINT1		10
#define XINT1		11

#define DMAC0		6
#define DMAC1		7
#define DMAC2		10
#define DMAC3		11
#define DMAC4		12
#define DMAC5		13


/*-------------------------------------------------------------*/
/* DEFINE DATA STRUCTURE FOR HOST PORT INTERFACE CONTROL REG   */
/*-------------------------------------------------------------*/
#define BOB		     	 0
#define SMOD		 1
#define DSPINT		 2
#define HINT		 3
#define XHPIA		 4

/******************************************************************/
/* Define Interrupt Flag and Interrupt Mask Registers             */
/******************************************************************/
#define IMR	*(volatile unsigned int*)0x00
#define IMR_ADDR		0x0 

#define IFR	*(volatile unsigned int*)0x01
#define IFR_ADDR		0x1

/******************************************************************/
/* NOTE:  YOU CAN ACCESS THESE REGISTERS IN THIS MANNER ONLY	  */
/* IF THE SUBADDRESS REGISTER HAS BEEN DEFINED ALREADY  		  */
/******************************************************************/

/******************************************************************/
/* MultiChannel Buffer Serial 0 defined for 54XX				  */
/******************************************************************/
#define SPCR10	*(volatile unsigned int*)0x39
#define SPCR10_ADDR	0x39

#define SPCR20	*(volatile unsigned int*)0x39
#define SPCR20_ADDR	0x39

#define DRR20	*(volatile unsigned int*)0x20
#define DRR20_ADDR	0x20

#define DRR10	*(volatile unsigned int*)0x21
#define DRR10_ADDR	0x21

#define DXR20	*(volatile unsigned int*)0x22
#define DXR20_ADDR	0x22

#define DXR10	*(volatile unsigned int*)0x23
#define DXR10_ADDR	0x23

/******************************************************************/
/* MultiChannel Buffer Serial 1 defined for 54XX				  */
/******************************************************************/
#define SPCR11	*(volatile unsigned int*)0x49
#define SPCR11_ADDR	0x49

#define SPCR21	*(volatile unsigned int*)0x49
#define SPCR21_ADDR	0x49

#define DRR21	*(volatile unsigned int*)0x40
#define DRR21_ADDR	0x40

#define DRR11	*(volatile unsigned int*)0x41
#define DRR11_ADDR	0x41

#define DXR21	*(volatile unsigned int*)0x42     

#define DXR21_ADDR	0x42

#define DXR11	*(volatile unsigned int*)0x43
#define DXR11_ADDR	0x43

#define SPCR12	*(volatile unsigned int*)0x35
#define SPCR12_ADDR	0x35 

/******************************************************************/
/* MultiChannel Buffer Serial 2 defined for 54XX				  */
/******************************************************************/
#define SPCR22	*(volatile unsigned int*)0x35
#define SPCR22_ADDR	0x35 

#define DRR22	*(volatile unsigned int*)0x30
#define DRR22_ADDR	0x30

#define DRR12	*(volatile unsigned int*)0x31
#define DRR12_ADDR	0x31

#define DXR22	*(volatile unsigned int*)0x32
#define DXR22_ADDR	0x32

#define DXR12	*(volatile unsigned int*)0x33
#define DXR12_ADDR	0x33
/******************************************************************/
/* Direct Memory Access defined for 54XX				          */
/******************************************************************/
#define DMPRE	  (0x54)
#define DMSBA	  (0x55)
#define DMSAI	  (0x56)
#define DMSRCP    (0x57)
#define DMDSTP    (0x57)
#define DMGSA     (0x57)
#define DMGDA     (0x57)
#define DMGCR     (0x57)
#define DMGFR     (0x57)
#define DMFRI(reg) ((reg) ? 0x57:0x57)
#define DMIDX(reg) ((reg) ? 0x57:0x57)
#define DMSRC(channel) ((channel) ? 0x57:0x57)
#define DMDST(channel) ((channel) ? 0x57:0x57)
#define DMCTR(channel) ((channel) ? 0x57:0x57)
#define DMSEFC(channel) ((channel) ? 0x57:0x57)
#define DMMCR(channel) ((channel) ? 0x57:0x57

#define DMA_REG_READ(dma_subaddress, channel) (DMSAI(channel)=dma_subaddress), *(volatile unsigned int*) DMFRI(channel))




/*----------------------------------------------------------------*/
/* Data bitfields Period for DMPRE                                */
/*----------------------------------------------------------------*/
#define DPRC5		13
#define DPRC5_SZ	 1

#define DPRC4		12
#define DPRC4_SZ	 1

#define DPRC3		11
#define DPRC3_SZ	 1

#define DPRC2		10
#define DPRC2_SZ	 1

#define DPRC1		 9
#define DPRC1_SZ	 1

#define DPRC0		 8
#define DPRC0_SZ	 1

#define INTSEL		 6
#define INTSEL_SZ    2

#define DE5			 5
#define DE5_SZ		 1

#define DE4			 4
#define DE4_SZ		 1

#define DE3			 3
#define DE3_SZ		 1

#define DE2			 2
#define DE2_SZ		 1

#define DE1			 1
#define DE1_SZ		 1

#define DE0			 0
#define DE0_SZ		 1

/*----------------------------------------------------------------*/
/* Data bitfields Period for DMSEFCn                              */
/*----------------------------------------------------------------*/
#define DSYN		12
#define DSYN_SZ		 4

#define FRAME_CNT    0
#define FRAME_CNT_SZ 8

/*----------------------------------------------------------------*/
/* Data bitfields Period for Mode Control Register                */
/*----------------------------------------------------------------*/
#define AUTOINIT	15
#define AUTOINIT_SZ	 1

#define DINM	    14
#define DINM_SZ      1

#define IMOD		13
#define IMOD_SZ      1

#define CTMOD		12
#define CTMOD_SZ     1

#define SIND		 8
#define SIND_SZ		 3

#define DMS			 6
#define DMS_SZ       2

#define DIND		 2
#define DIND_SZ      3

#define DMD			 0
#define DMD_SZ       2

/*******************************************************************/
/* TIMER REGISTER ADDRESSES   (TIM0 = Timer 0, TIM1 = Timer 1      */
/* Defined for all devices                                         */
/*******************************************************************/
#define TIM_ADDR(port) (port ? 0x30 : 0x24)
#define TIM(port)	*(volatile unsigned int*)TIM_ADDR(port)

#define PRD_ADDR(port)		(port ? 0x31 : 0x25)
#define PRD(port)	*(volatile unsigned int*)PRD_ADDR(port)

#define TCR_ADDR(port)		(port ? 0x32 : 0x26)
#define TCR(port)	*(volatile unsigned int*)TCR_ADDR(port)

/*********************************************************************/
/* EXTERNAL BUS CONTROL REGISTERS                                    */
/*********************************************************************/
#define BSCR	*(volatile unsigned int*)0x29
#define BSCR_ADDR	0x29

#define SWCR	*(volatile unsigned int*)0x2B
#define SWCR_ADDR	0x2B

#define SWWSR	*(volatile unsigned int*)0x28
#define SWWSR_ADDR	0x28

/*********************************************************************/
/* HOST PORT INTERFACE REGISTER ADDRESS                              */
/* Defined for C54XX					                             */
/*********************************************************************/
#define HPIC	*(volatile unsigned int*)0x2C
#define HPIC_ADDR	0x2C
#define HPI_ADDR	0x1000 

/*********************************************************************/
/* Defined flags for use in setting control for HPI host interface   */
/* control pins                                                      */
/* The value of these constants is their relative bit position in    */
/* the control structure for the host side of the HPI interface      */
/*********************************************************************/
#define HAS_PIN		0    
#define HBIL_PIN	   1    
#define HCNTL0_PIN	2    
#define HCNTL1_PIN	3
#define HCS_PIN		4
#define HD0_PIN		5
#define HDS1_PIN	   6
#define HDS2_PIN  	7
#define HINT_PIN  	8
#define HRDY_PIN	   9
#define HRW_PIN		10

/*********************************************************************/
/* CLOCK MODE REGISTER ADDRESS                                       */
/* Defined for C54XX				                                       */
/*********************************************************************/
#define CLKMD 	*(volatile unsigned int*)0x58
#define CLKMD_ADDR	0x58

/*********************************************************************/
/* Extended Program Counter -XPC register                            */
/*********************************************************************/
extern volatile unsigned int XPC;
#define XPC	*(volatile unsigned int*)0x1e
#define XPC_ADDR		0x1e

/*********************************************************************/
/* Program Control and Status Registers (PMST, ST0, ST1)             */
/*********************************************************************/
#define PMST	*(volatile unsigned int*)0x1d
#define PMST_ADDR	0x1d

#define ST0	*(volatile unsigned int*)0x06
#define ST0_ADDR	0x06

#define ST1	*(volatile unsigned int*)0x07
#define ST1_ADDR	0x07

/*********************************************************************/
/* General-purpose I/O pins control registers (GPIOCR, GPIOSR)       */
/*********************************************************************/
#define GPIOCR	*(volatile unsigned int*)0x3C
#define GPIOCR_ADDR	0x3C

#define GPIOSR	*(volatile unsigned int*)0x3D
#define GPIOSR_ADDR	0x3D

#define __54XXREGS
#endif