dma54xx.h

5416完整例程

/*****************************************************************/
/* Copyright (c) Texas Instruments, Incorporated  2000           */
/*****************************************************************/
/******************************************************************************/
/*  DMA54XX.H - DMA5402 routines header file.                                 */
/*                                                                            */
/*     This module provides the devlib implementation for the DMAC            */
/*     on the TMS320C54XX DSP.                                                */
/*                                                                            */
/*  MACRO FUNCTIONS:                                                          */
/*     DMA_ENABLE 		- enable selected DMA channel                         */                      
/*     DMA_DISABLE 		- disable selected DMA channel                        */
/*     DMA_AUTO_ENABLE 		- enable selected DMA channel with auto-init       */
/*     DMA_FREE_RUNNING 	- enable DMA free running                          */
/*     DMA_NO_FREE_RUNNING 	- disable DMA free running                      */
/*     DMA_FRAMECOUNT 		- set number of frames in multi-frame transfer     */
/*     DMA_INTMASK_ENABLE 	- enable DMA interrupt                             */
/*     DMA_INTMASK_DISABLE 	- disable DMA interrupt                         */
/*     DMA_DMS_SELECT 		- set Source Space Select                          */
/*     DMA_DMD_SELECT 		- set Destination Space Select                     */
/*                                                                            */
/*  FUNCTIONS:                                                                */
/*     dma_init 		 -  Initialize channel specific control registers        */
/*     dma_global_init() - Initialize global control registers.               */
/*     dma_reset_all()       - Resets indicated DMA channel                       */
/*                                                                            */
/*                                                                            */
/*  AUTHOR:                                                                   */
/*     Stefan Haas                                                            */
/*                                                                            */
/*  REVISION HISTORY:                                                         */
/*                                                                            */
/*    DATE       AUTHOR                       DESCRIPTION                     */
/*   -------   -------------      ------------------------------------------  */
/*   13OCT98   St Haas            Original.                                   */
/*                                                                            */
/******************************************************************************/
#ifndef _DMA_H_
#define _DMA_H_


#include "regs54xx.h"

/*----------------------------------------------------------------------------*/
/* DEFINES                                                                    */
/*----------------------------------------------------------------------------*/


/* CONFIGURATION REGISTER BIT and BITFIELD values */

/* DMA Priority and Enable Contol Regiser (DMPRE) */

#define FREE_OFF			0x00     /* DMA stops after the DMA xfer complet. */ 
#define FREE_ON				0x01     /* DMA runs free, even if device halted  */

#define LOW_PRIORITY		0x00     /* Lowest priority for DMA channel       */
#define HIGH_PRIORITY		0x01     /* Highest priority for DMA channel      */

#define INTSEL_00			0x00     /* RINT0,XINT0,RINT2,XINT2,RINT1,XINT1,  */
						   /* DMAC4,DMAC5                           */
#define INTSEL_01			0x01     /* RINT0,XINT0,RINT2,XINT2,DMAC2,DMAC3,  */
						   /* DMAC4,DMAC5                           */
#define INTSEL_10			0x10     /* RINT0,XINT0,DMAC0,DMAC1,DMAC2,DMAC3,  */
						   /* DMAC4,DMAC5                           */
#define INTSEL_11			0x11	   /* reserved */  

#define CHAN_DISABLE		0x00     /* DMA channel is disabled               */
#define CHAN_ENABLE		0x01     /* DMA channel is enable                 */

/* DMA Sync Event and Frame Count register for channel n DMSEFCn */
/* question marks: values unclear at that time, MCBSP-Documentation error ??? */

#define DSYNC_NO            0x00     /* No synchronization (DMA Xfer sync ev) */
#define DSYNC_REVT0         0x01     /* sync to McBSP0 receive event          */
#define DSYNC_XEVT0         0x02     /* sync to McBSP0 transmit event         */

/* NOTE: The following two events are reserved on the 54XX                    */
#define DSYNC_REVT2         0x03     /* sync to McBSP2 receive event          */
#define DSYNC_XEVT2         0x04     /* sync to McBSP2 transmit event         */

#define DSYNC_REVT1         0x05     /* sync to McBSP1 receive event          */
#define DSYNC_XEVT1         0x06     /* sync to McBSP1 transmit event         */

/* NOTE: The following six events are reserved on the 54XX                    */
#define DSYNC_REVT0A        0x07     /* sync to McBSP0 receive eventA         */
#define DSYNC_XEVT0A        0x08     /* sync to McBSP0 transmit eventA        */
#define DSYNC_REVT2A        0x09     /* sync to McBSP2 receive eventA  ?      */
#define DSYNC_XEVT2A        0x0A     /* sync to McBSP2 transmit eventA   ?    */
#define DSYNC_REVT1A        0x0B     /* sync to McBSP1 receive eventA  ?      */
#define DSYNC_XEVT1A        0x0C     /* sync to McBSP1 transmit eventA   ?    */

#define DSYNC_TIMER         0x0D     /* sync to Timer interrupt                   */
#define DSYNC_TIMER0        0x0D     /* sync to Timer 0 interrupt                 */
#define DSYNC_INT4          0x0E     /* sync to external interrupt 3              */
#define DSYNC_TIMER1        0x0F     /* sync to Timer 1 interrupt                 */

#define DBLW_DISABLE        0x00     /* Double word transfer mode is disabled */
#define DBLW_ENABLE         0x01     /* Double word transfer mode is enabled  */
                            
#define FRAMECOUNT_MAX		0x0FF    /* max number of frames in multi-frame   */

/* DMA Mode Control Register Summary */	 

#define AUTOINIT_DISABLE	0x00     /* auto-initialization mode is disabled  */
#define AUTOINIT_ENABLE		0x01     /* auto-initialization mode is enabled   */

#define DINM_DISABLE		0x00     /* DMA interrupt is disabled             */
#define DINM_ENABLE		0x01     /* DMA interrupt is enabled              */

#define IMOD_BLOCK		0x00     /* DMA Int occurs at the end of the block*/
#define IMOD_HALFBLOCK        0x01     /* DMA Int occurs each half block        */

#define CTMOD_DEC			0x00     /* Decrement counter mode                */
#define CTMOD_NODEC_ABU		0x01     /* Non-decrement mode or ABU mode        */

#define INDEXMODE_NOMOD		    0x00 /* No modify (Index mode)                */
#define INDEXMODE_INC		    0x01 /* Post increment index mode             */
#define INDEXMODE_DEC		    0x02 /* Post decrement index mode             */
#define INDEXMODE_INC_IDX0_FRI0   0x03 /* Post incr with index & frame offset 0 */
#define INDEXMODE_INC_IDX1_FRI1   0x04 /* Post incr with index & frame offset 1 */

#define SPACE_PROG		0x00     /* DMA Program Space Select              */
#define SPACE_DATA		0x01     /* DMA Data Space Select                 */
#define SPACE_IO			0x02     /* DMA I/O Space Select                  */ 


#define DMCTR_MAX			0x0FFFF  /* max value of DMA Counter Register     */
#define DMIDX_MAX			0x0FFFF  /* max value of DMA Index Registers      */
#define DMFRI_MAX			0x0FFFF  /* max value of DMA Frame Idx Registers  */
/* define Global Reload Registers ???*/


#define DMA_CH0			0x00     /* DMA Channel 0                         */
#define DMA_CH1			0x01     /* DMA Channel 1                         */
#define DMA_CH2			0x02     /* DMA Channel 2                         */
#define DMA_CH3			0x03     /* DMA Channel 3                         */
#define DMA_CH4			0x04     /* DMA Channel 4                         */
#define DMA_CH5			0x05     /* DMA Channel 5                         */  



#if _INLINE
#define __INLINE static inline